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modified transceiver configuration files

main
Shrutika Redkar 2016-08-10 14:59:38 -04:00
parent b8f4e1c0aa
commit 829e4155ca
2 changed files with 5 additions and 3 deletions
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6
library/xilinx/axi_adxcvr/axi_adxcvr.v
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@ -695,7 +695,7 @@ module axi_adxcvr (
.up_sel (up_cm_sel),
.up_enb (up_cm_enb),
.up_rdata_in (16'd0),
.up_ready_in (1'd0),
.up_ready_in (1'd1),
.up_rdata (up_cm_rdata_0),
.up_ready (up_cm_ready_0),
.up_rdata_out (up_cm_rdata_0_s),
@ -716,7 +716,7 @@ module axi_adxcvr (
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_rdata_in (16'd0),
.up_ready_in (1'd0),
.up_ready_in (1'd1),
.up_rdata (up_es_rdata_0),
.up_ready (up_es_ready_0),
.up_rdata_out (up_es_rdata_0_s),
@ -758,7 +758,7 @@ module axi_adxcvr (
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_rdata_in (16'd0),
.up_ready_in (1'd0),
.up_ready_in (1'd1),
.up_rdata (up_ch_rdata_0),
.up_ready (up_ch_ready_0),
.up_rdata_out (up_ch_rdata_0_s),

2
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -64,11 +64,13 @@ xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]
set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_clk \
-of_objects [ipx::current_core]]]
ipx::add_memory_map {s_axi} [ipx::current_core]
set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]