transceiver split up outside qsys
Rejeesh Kutty
parent
8c0d74aa90
commit
825fddd034
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// This may be done inside QSYS, but it does a bad job of connecting the same signal
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// to multiple inputs, concatenation, bus splits and numerous connections
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// in-between. Also signal tap doesn't behave nicely within the system.
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`timescale 1ns/100ps
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module sys_xcvr (
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// io
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up_clk,
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up_rstn,
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rx_ref_clk,
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rx_d,
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tx_ref_clk,
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tx_d,
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rst,
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rx_clk,
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rx_rstn,
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rx_sysref,
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rx_ip_sync,
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rx_ip_sof,
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rx_ip_data,
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rx_ready,
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rx_int,
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tx_clk,
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tx_rstn,
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tx_sysref,
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tx_ip_sync,
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tx_ip_data,
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tx_ready,
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tx_int,
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stp_clk,
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stp_data,
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stp_trigger);
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// parameters are not used--
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parameter PCORE_NUM_OF_TX_LANES = 4;
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parameter PCORE_NUM_OF_RX_LANES = 4;
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parameter PCORE_ST_DATA_WIDTH = 32;
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parameter PCORE_ST_TRIGGER_WIDTH = 4;
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// io
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input up_clk;
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input up_rstn;
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input rx_ref_clk;
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input [ 3:0] rx_d;
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input tx_ref_clk;
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output [ 3:0] tx_d;
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input rst;
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output rx_clk;
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input rx_rstn;
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input rx_sysref;
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output rx_ip_sync;
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output [ 3:0] rx_ip_sof;
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output [127:0] rx_ip_data;
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output [ 3:0] rx_ready;
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output rx_int;
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output tx_clk;
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input tx_rstn;
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input tx_sysref;
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input tx_ip_sync;
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input [127:0] tx_ip_data;
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output [ 3:0] tx_ready;
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output tx_int;
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output stp_clk;
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output [ 31:0] stp_data;
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output [ 3:0] stp_trigger;
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// internal signals
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wire [ 3:0] rx_analogreset;
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wire [ 3:0] rx_cal_busy;
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wire rx_bit_reversal;
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wire rx_byte_reversal;
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wire [ 3:0] rx_lane_polarity;
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wire [ 3:0] rx_lane_powerdown;
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wire [ 3:0] rx_digitalreset;
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wire [ 3:0] rx_islockedtodata;
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wire [ 3:0] rx_patternalign_en;
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wire rx_dev_lane_aligned;
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wire [ 3:0] rx_pcfifo_empty;
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wire [ 3:0] rx_pcfifo_full;
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wire [ 3:0] rx_pcs_valid;
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wire [ 15:0] rx_pcs_disperr;
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wire [ 15:0] rx_pcs_errdetect;
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wire [ 15:0] rx_pcs_kchar;
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wire [127:0] rx_pcs_data;
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wire [ 0:0] tx_xcvr_clk;
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wire [ 3:0] tx_pll_locked;
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wire tx_pll_powerdown;
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wire [ 3:0] tx_analogreset;
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wire [ 3:0] tx_cal_busy;
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wire tx_bit_reversal;
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wire tx_byte_reversal;
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wire [ 3:0] tx_lane_polarity;
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wire [ 3:0] tx_lane_powerdown;
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wire [ 3:0] tx_digitalreset;
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wire [ 3:0] tx_elecidle;
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wire tx_dev_syncn;
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wire [ 3:0] tx_pcfifo_empty;
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wire [ 3:0] tx_pcfifo_full;
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wire [ 15:0] tx_pcs_kchar;
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wire [127:0] tx_pcs_data;
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// instantiations
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sys_xcvr_rx_pll i_rx_pll (
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.locked (),
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.outclk_0 (rx_clk),
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.refclk (rx_ref_clk),
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.rst (rst));
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sys_xcvr_tx_pll i_tx_pll (
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.locked (),
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.outclk_0 (tx_clk),
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.refclk (tx_ref_clk),
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.rst (rst));
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sys_xcvr_tx_lane_pll i_tx_lane_pll (
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.pll_cal_busy (),
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.pll_locked (tx_pll_locked),
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.pll_powerdown (tx_pll_powerdown),
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.pll_refclk0 (tx_ref_clk),
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.tx_serial_clk (tx_xcvr_clk));
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sys_xcvr_rstcntrl i_rstcntrl (
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.clock (up_clk),
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.pll_locked (tx_pll_locked),
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.pll_powerdown (tx_pll_powerdown),
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.pll_select (1'd0),
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.reset (rst),
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.rx_analogreset (rx_analogreset),
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.rx_cal_busy (rx_cal_busy),
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.rx_digitalreset (rx_digitalreset),
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.rx_is_lockedtodata (rx_islockedtodata),
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.rx_ready (rx_ready),
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.tx_analogreset (tx_analogreset),
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.tx_cal_busy (tx_cal_busy),
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.tx_digitalreset (tx_digitalreset),
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.tx_ready (tx_ready));
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sys_xcvr_core i_core (
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.jesd204_rx_pcs_data (rx_pcs_data),
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.jesd204_rx_pcs_data_valid (rx_pcs_valid),
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.jesd204_rx_pcs_disperr (rx_pcs_disperr),
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.jesd204_rx_pcs_errdetect (rx_pcs_errdetect),
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.jesd204_rx_pcs_kchar_data (rx_pcs_kchar),
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.jesd204_tx_pcs_data (tx_pcs_data),
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.jesd204_tx_pcs_kchar_data (tx_pcs_kchar),
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.patternalign_en (rx_patternalign_en),
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.phy_csr_rx_pcfifo_empty (rx_pcfifo_empty),
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.phy_csr_rx_pcfifo_full (rx_pcfifo_full),
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.phy_csr_tx_pcfifo_empty (tx_pcfifo_empty),
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.phy_csr_tx_pcfifo_full (tx_pcfifo_full),
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.phy_tx_elecidle (tx_elecidle),
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.rx_analogreset (rx_analogreset),
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.rx_cal_busy (rx_cal_busy),
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.rx_csr_bit_reversal (rx_bit_reversal),
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.rx_csr_byte_reversal (rx_byte_reversal),
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.rx_csr_lane_polarity (rx_lane_polarity),
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.rx_csr_lane_powerdown (rx_lane_powerdown),
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.rx_digitalreset (rx_digitalreset),
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.rx_islockedtodata (rx_islockedtodata),
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.rx_pll_ref_clk (rx_ref_clk),
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.rx_serial_data (rx_d),
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.rx_seriallpbken (4'd0),
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.rxlink_clk (rx_clk),
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.rxlink_rst_n_reset_n (rx_rstn),
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.rxphy_clk (),
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.tx_analogreset (tx_analogreset),
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.tx_cal_busy (tx_cal_busy),
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.tx_csr_bit_reversal (tx_bit_reversal),
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.tx_csr_byte_reversal (tx_byte_reversal),
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.tx_csr_lane_polarity (tx_lane_polarity),
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.tx_csr_lane_powerdown (tx_lane_powerdown),
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.tx_digitalreset (tx_digitalreset),
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.tx_serial_clk0_ch0 (tx_xcvr_clk),
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.tx_serial_clk0_ch1 (tx_xcvr_clk),
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.tx_serial_clk0_ch2 (tx_xcvr_clk),
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.tx_serial_clk0_ch3 (tx_xcvr_clk),
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.tx_serial_data (tx_d),
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.txlink_clk (tx_clk),
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.txlink_rst_n_reset_n (tx_rstn),
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.txphy_clk ());
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sys_xcvr_rx_ip i_rx_ip (
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.alldev_lane_aligned (rx_dev_lane_aligned),
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.csr_bit_reversal (rx_bit_reversal),
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.csr_byte_reversal (rx_byte_reversal),
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.csr_cf (),
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.csr_cs (),
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.csr_f (),
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.csr_hd (),
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.csr_k (),
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.csr_l (),
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.csr_lane_polarity (rx_lane_polarity),
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.csr_lane_powerdown (rx_lane_powerdown),
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.csr_m (),
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.csr_n (),
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.csr_np (),
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.csr_rx_testmode (),
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.csr_s (),
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.dev_lane_aligned (rx_dev_lane_aligned),
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.dev_sync_n (rx_ip_sync),
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.jesd204_rx_avs_chipselect (1'd0),
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.jesd204_rx_avs_address (8'd0),
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.jesd204_rx_avs_read (1'd0),
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.jesd204_rx_avs_readdata (),
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.jesd204_rx_avs_waitrequest (),
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.jesd204_rx_avs_write (1'd0),
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.jesd204_rx_avs_writedata (32'd0),
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.jesd204_rx_avs_clk (up_clk),
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.jesd204_rx_avs_rst_n (up_rstn),
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.jesd204_rx_dlb_data (128'd0),
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.jesd204_rx_dlb_data_valid (4'd0),
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.jesd204_rx_dlb_disperr (16'd0),
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.jesd204_rx_dlb_errdetect (16'd0),
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.jesd204_rx_dlb_kchar_data (16'd0),
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.jesd204_rx_frame_error (1'd0),
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.jesd204_rx_int (rx_int),
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.jesd204_rx_link_data (rx_ip_data),
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.jesd204_rx_link_valid (),
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.jesd204_rx_link_ready (1'd0),
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.jesd204_rx_pcs_data (rx_pcs_data),
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.jesd204_rx_pcs_data_valid (rx_pcs_valid),
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.jesd204_rx_pcs_disperr (rx_pcs_disperr),
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.jesd204_rx_pcs_errdetect (rx_pcs_errdetect),
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.jesd204_rx_pcs_kchar_data (rx_pcs_kchar),
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.patternalign_en (rx_patternalign_en),
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.phy_csr_rx_pcfifo_empty (rx_pcfifo_empty),
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.phy_csr_rx_pcfifo_full (rx_pcfifo_full),
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.rx_cal_busy (rx_cal_busy),
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.rx_islockedtodata (rx_islockedtodata),
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.rxlink_clk (rx_clk),
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.rxlink_rst_n_reset_n (rx_rstn),
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.sof (rx_ip_sof),
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.somf (),
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.sysref (rx_sysref));
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sys_xcvr_tx_ip i_tx_ip (
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.csr_bit_reversal (tx_bit_reversal),
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.csr_byte_reversal (tx_byte_reversal),
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.csr_cf (),
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.csr_cs (),
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.csr_f (),
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.csr_hd (),
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.csr_k (),
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.csr_l (),
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.csr_lane_polarity (),
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.csr_lane_powerdown (),
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.csr_m (),
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.csr_n (),
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.csr_np (),
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.csr_s (),
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.csr_tx_testmode (),
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.csr_tx_testpattern_a (),
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.csr_tx_testpattern_b (),
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.csr_tx_testpattern_c (),
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.csr_tx_testpattern_d (),
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.dev_sync_n (tx_dev_syncn),
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.jesd204_tx_avs_chipselect (1'd0),
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.jesd204_tx_avs_address (8'd0),
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.jesd204_tx_avs_read (1'd0),
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.jesd204_tx_avs_readdata (),
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.jesd204_tx_avs_waitrequest (),
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.jesd204_tx_avs_write (1'd0),
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.jesd204_tx_avs_writedata (32'd0),
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.jesd204_tx_avs_clk (up_clk),
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.jesd204_tx_avs_rst_n (up_rstn),
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.jesd204_tx_frame_error (1'd0),
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.jesd204_tx_frame_ready (),
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.jesd204_tx_int (tx_int),
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.jesd204_tx_link_data (tx_ip_data),
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.jesd204_tx_link_valid (1'b1),
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.jesd204_tx_link_ready (),
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.jesd204_tx_pcs_data (tx_pcs_data),
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.jesd204_tx_pcs_kchar_data (tx_pcs_kchar),
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.mdev_sync_n (tx_dev_syncn),
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.phy_csr_tx_pcfifo_empty (tx_pcfifo_empty),
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.phy_csr_tx_pcfifo_full (tx_pcfifo_full),
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.phy_tx_elecidle (tx_elecidle),
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.pll_locked (tx_pll_locked),
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.sync_n (tx_ip_sync),
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.sysref (tx_sysref),
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.tx_cal_busy (tx_cal_busy),
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.txlink_clk (tx_clk),
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.txlink_rst_n_reset_n (tx_rstn));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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