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axi_dacfifo: Fix resets 

DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
main
Istvan Csomortani 2016-05-17 11:30:41 +03:00
parent 578376c8fe
commit 81ade7f26c
4 changed files with 22 additions and 21 deletions
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18
library/axi_dacfifo/axi_dacfifo.v
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@ -53,7 +53,7 @@ module axi_dacfifo (
// dac interface
dac_clk,
dac_reset,
dac_rst,
dac_valid,
dac_data,
dac_dunf,
@ -134,7 +134,7 @@ module axi_dacfifo (
// dac interface
input dac_clk;
input dac_reset;
input dac_rst;
input dac_valid;
output [(DAC_DATA_WIDTH-1):0] dac_data;
output dac_dunf;
@ -190,10 +190,6 @@ module axi_dacfifo (
input [(AXI_DATA_WIDTH-1):0] axi_rdata;
output axi_rready;
// internal registers
reg dma_dacrst_m1 = 1'b0;
reg dma_dacrst_m2 = 1'b0;
// internal signals
wire [(AXI_DATA_WIDTH-1):0] axi_wr_data_s;
@ -204,15 +200,7 @@ module axi_dacfifo (
wire axi_rd_valid_s;
wire [31:0] axi_rd_lastaddr_s;
wire axi_xfer_req_s;
wire dma_rst_s;
// DAC reset the DMA side too
always @(posedge dma_clk) begin
dma_dacrst_m1 <= dac_reset;
dma_dacrst_m2 <= dma_dacrst_m1;
end
assign dma_rst_s = dma_dacrst_m2;
wire [(DAC_DATA_WIDTH-1):0] dac_data_s;
wire dma_ready_s;
@ -227,7 +215,6 @@ module axi_dacfifo (
.AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT)
) i_wr (
.dma_clk (dma_clk),
.dma_rst (dma_rst_s),
.dma_data (dma_data),
.dma_ready (dma_ready_s),
.dma_valid (dma_valid),
@ -306,6 +293,7 @@ module axi_dacfifo (
.axi_dready (axi_rd_ready_s),
.axi_xfer_req (axi_xfer_req_s),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_valid (dac_valid),
.dac_data (dac_data_s),
.dac_xfer_out (dac_xfer_out),

3
library/axi_dacfifo/axi_dacfifo_dac.v
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@ -48,6 +48,7 @@ module axi_dacfifo_dac (
axi_xfer_req,
dac_clk,
dac_rst,
dac_valid,
dac_data,
dac_xfer_out,
@ -81,6 +82,7 @@ module axi_dacfifo_dac (
// dac read
input dac_clk;
input dac_rst;
input dac_valid;
output [(DAC_DATA_WIDTH-1):0] dac_data;
output dac_xfer_out;
@ -100,7 +102,6 @@ module axi_dacfifo_dac (
reg axi_almost_empty = 1'b0;
reg axi_dwovf = 1'b0;
reg dac_rst = 'd0;
reg dac_rd = 'd0;
reg dac_rd_d = 'd0;
reg [(DAC_DATA_WIDTH-1):0] dac_rdata_d = 'd0;

20
library/axi_dacfifo/axi_dacfifo_wr.v
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@ -44,7 +44,6 @@ module axi_dacfifo_wr (
// dma fifo interface
dma_clk,
dma_rst,
dma_data,
dma_ready,
dma_valid,
@ -115,7 +114,6 @@ module axi_dacfifo_wr (
// dma fifo interface
input dma_clk;
input dma_rst;
input [(DMA_DATA_WIDTH-1):0] dma_data;
output dma_ready;
input dma_valid;
@ -165,6 +163,8 @@ module axi_dacfifo_wr (
reg [(AXI_MADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0;
reg [(AXI_MADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0;
reg dma_ready = 'd0;
reg dma_rst_m1 = 1'b0;
reg dma_rst_m2 = 1'b0;
reg [ 2:0] axi_xfer_req_m = 3'b0;
reg [ 2:0] axi_xfer_last_m = 3'b0;
@ -188,10 +188,13 @@ module axi_dacfifo_wr (
reg axi_mem_last_d = 1'b0;
reg [ 3:0] axi_wvalid_cntr = 4'b0;
// internal signal
wire [(DMA_MADDRESS_WIDTH-1):0] dma_mem_addr_diff_s;
wire [(DMA_MADDRESS_WIDTH-1):0] dma_mem_raddr_s;
wire dma_rst_s;
wire [(DMA_MADDRESS_WIDTH-1):0] axi_mem_waddr_s;
wire axi_req_s;
wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s;
@ -234,10 +237,19 @@ module axi_dacfifo_wr (
end
endfunction
// syncronize the AXI interface reset
always @(posedge dma_clk) begin
dma_rst_m1 <= ~axi_resetn;
dma_rst_m2 <= dma_rst_m1;
end
assign dma_rst_s = dma_rst_m2;
// write address generation for the asymetric memory
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
if (dma_rst_s == 1'b1) begin
dma_mem_waddr <= 8'h0;
dma_mem_waddr_g <= 8'h0;
end else begin
@ -255,7 +267,7 @@ module axi_dacfifo_wr (
{dma_mem_raddr, 3'b0};
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
if (dma_rst_s == 1'b1) begin
dma_mem_addr_diff <= 'b0;
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;

2
projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
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@ -67,7 +67,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
ad_connect axi_resetn axi_rstgen/peripheral_aresetn
ad_connect axi_resetn axi_dacfifo/axi_resetn
ad_connect axi_resetn axi_ddr_cntrl/aresetn
ad_connect dac_rst axi_dacfifo/dac_reset
ad_connect dac_rst axi_dacfifo/dac_rst
ad_connect dac_rst axi_rstgen/ext_reset_in
## interfaces