diff --git a/library/util_pmod_adc/util_pmod_adc.v b/library/util_pmod_adc/util_pmod_adc.v
index e432c4278..b0d59b83f 100644
--- a/library/util_pmod_adc/util_pmod_adc.v
+++ b/library/util_pmod_adc/util_pmod_adc.v
@@ -63,12 +63,11 @@ module util_pmod_adc (
   // clock and reset signals
 
   clk,
-  reset,
+  resetn,
 
   // dma interface
   adc_data,
   adc_valid,
-  adc_enable,
   adc_dbg,
 
   // adc interface (clk, data, cs and conversion start)
@@ -108,13 +107,12 @@ module util_pmod_adc (
   // clock and reset signals
 
   input           clk;                          // system clock (100 MHz)
-  input           reset;                        // active high reset signal
+  input           resetn;                       // active low reset signal
 
   // dma interface
 
   output  [15:0]  adc_data;
   output          adc_valid;
-  output          adc_enable;
   output  [24:0]  adc_dbg;
 
   // adc interface
@@ -150,12 +148,11 @@ module util_pmod_adc (
   // Assign/Always Blocks
 
   assign adc_sclk   = adc_spi_clk & adc_clk_en;
-  assign adc_enable = 1'b1;
 
   // spi clock generation
   always @(posedge clk) begin
     adc_clk_cnt <= adc_clk_cnt + 1;
-    if (adc_clk_cnt == ((ADC_CLK_DIVIDE/2)-1)) begin 
+    if (adc_clk_cnt == ((ADC_CLK_DIVIDE/2)-1)) begin
       adc_clk_cnt <= 0;
       adc_spi_clk <= ~adc_spi_clk;
     end
@@ -165,7 +162,7 @@ module util_pmod_adc (
 
   always @(posedge clk)
   begin
-    if(reset == 1'b1) begin
+    if(resetn == 1'b0) begin
       adc_tconvst_cnt  <= ADC_CONVST_CNT;
       adc_tconvert_cnt <= ADC_CONVERT_CNT;
       adc_tquiet_cnt   <= ADC_TQUITE_CNT;
@@ -215,7 +212,7 @@ module util_pmod_adc (
   // update the ADC current state and the control signals
 
   always @(posedge clk) begin
-    if(reset == 1'b1) begin
+    if(resetn == 1'b0) begin
       adc_state <= ADC_SW_RESET;
       adc_dbg <= 1'b0;
     end
diff --git a/library/util_pmod_adc/util_pmod_adc_ip.tcl b/library/util_pmod_adc/util_pmod_adc_ip.tcl
index e6876d819..907031f01 100644
--- a/library/util_pmod_adc/util_pmod_adc_ip.tcl
+++ b/library/util_pmod_adc/util_pmod_adc_ip.tcl
@@ -5,8 +5,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
 
 adi_ip_create util_pmod_adc
 adi_ip_files util_pmod_adc [list \
-  "util_pmod_adc_constr.xdc" \
-  "util_pmod_adc.v"
+  "util_pmod_adc.v" \
+  "util_pmod_adc_constr.xdc"
 ]
 
 adi_ip_properties_lite util_pmod_adc
@@ -14,11 +14,5 @@ adi_ip_properties_lite util_pmod_adc
 adi_ip_constraints util_pmod_adc [list \
   "util_pmod_adc_constr.xdc" ]
 
-# set reset polarity to high
-set reset_inf [ipx::get_bus_interfaces "signal_reset" -of_objects [ipx::current_core]]
-set reset_polarity [ipx::get_bus_parameters "POLARITY" -of_objects $reset_inf]
-set_property value "ACTIVE_HIGH" $reset_polarity
-
 ipx::save_core [ipx::current_core]
 
-
diff --git a/projects/cftl_cip/common/cftl_cip_bd.tcl b/projects/cftl_cip/common/cftl_cip_bd.tcl
index ac30f0cc9..44b39ec9b 100644
--- a/projects/cftl_cip/common/cftl_cip_bd.tcl
+++ b/projects/cftl_cip/common/cftl_cip_bd.tcl
@@ -37,7 +37,7 @@ ad_connect sys_cpu_clk pmod_spi_dma/fifo_wr_clk
 ad_connect sys_cpu_clk pmod_spi_core/clk
 ad_connect sys_cpu_clk pmod_gpio_core/ref_clk
 
-ad_connect pmod_spi_core/reset sys_rstgen/peripheral_reset
+ad_connect pmod_spi_core/resetn sys_rstgen/peripheral_aresetn
 
 ad_connect  pmod_spi_core/adc_data pmod_spi_dma/fifo_wr_din
 ad_connect  pmod_spi_core/adc_valid pmod_spi_dma/fifo_wr_en