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util_adc_pack: removed latches

main
Adrian Costina 2014-10-17 15:40:16 +03:00
parent 2600b1f359
commit 819a3d0802
1 changed files with 78 additions and 86 deletions
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34
library/util_adc_pack/util_adc_pack.v
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@ -123,13 +123,15 @@ module util_adc_pack (
output dvalid;
output dsync;
reg [(DATA_WIDTH*CHANNELS-1):0] packed_data = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_0 = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_1 = 0;
reg [3:0] enable_cnt;
reg [2:0] enable_cnt_0;
reg [2:0] enable_cnt_1;
reg [255:0] packed_data = 0;
reg [127:0] temp_data_0 = 0;
reg [127:0] temp_data_1 = 0;
reg [7:0] path_enabled = 0;
reg [7:0] path_enabled_d1 = 0;
reg [6:0] counter_0 = 0;
@ -137,7 +139,6 @@ module util_adc_pack (
reg [7:0] en2 = 0;
reg [7:0] en4 = 0;
reg dvalid = 0;
reg chan_valid = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0;
reg [(DATA_WIDTH-1):0] chan_data_0_r;
@ -149,7 +150,10 @@ module util_adc_pack (
reg [(DATA_WIDTH-1):0] chan_data_6_r;
reg [(DATA_WIDTH-1):0] chan_data_7_r;
wire chan_valid;
assign dsync = dvalid;
assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
always @(posedge clk)
begin
@ -167,7 +171,8 @@ module util_adc_pack (
always @(posedge clk)
begin
chan_valid <= chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
if(chan_valid == 1'b1)
begin
chan_data_0_r <= chan_data_0;
chan_data_1_r <= chan_data_1;
chan_data_2_r <= chan_data_2;
@ -177,10 +182,9 @@ module util_adc_pack (
chan_data_6_r <= chan_data_6;
chan_data_7_r <= chan_data_7;
end
end
always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3, chan_valid)
begin
if(chan_valid == 1'b1)
always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 )
begin
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r;
@ -213,15 +217,8 @@ module util_adc_pack (
default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
endcase
end
else
begin
temp_data_0 = 0;
end
end
always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7, chan_valid)
begin
if(chan_valid == 1'b1)
always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7)
begin
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r;
@ -254,11 +251,6 @@ module util_adc_pack (
default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
endcase
end
else
begin
temp_data_1 = 0;
end
end
always @(enable_cnt)
begin