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util_adc_pack: removed latches

main
Adrian Costina 2014-10-17 15:40:16 +03:00
parent 2600b1f359
commit 819a3d0802
1 changed files with 78 additions and 86 deletions
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164
library/util_adc_pack/util_adc_pack.v
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@ -123,13 +123,15 @@ module util_adc_pack (
output dvalid; output dvalid;
output dsync; output dsync;
reg [(DATA_WIDTH*CHANNELS-1):0] packed_data = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_0 = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_1 = 0;
reg [3:0] enable_cnt; reg [3:0] enable_cnt;
reg [2:0] enable_cnt_0; reg [2:0] enable_cnt_0;
reg [2:0] enable_cnt_1; reg [2:0] enable_cnt_1;
reg [255:0] packed_data = 0;
reg [127:0] temp_data_0 = 0;
reg [127:0] temp_data_1 = 0;
reg [7:0] path_enabled = 0; reg [7:0] path_enabled = 0;
reg [7:0] path_enabled_d1 = 0; reg [7:0] path_enabled_d1 = 0;
reg [6:0] counter_0 = 0; reg [6:0] counter_0 = 0;
@ -137,7 +139,6 @@ module util_adc_pack (
reg [7:0] en2 = 0; reg [7:0] en2 = 0;
reg [7:0] en4 = 0; reg [7:0] en4 = 0;
reg dvalid = 0; reg dvalid = 0;
reg chan_valid = 0;
reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0; reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0;
reg [(DATA_WIDTH-1):0] chan_data_0_r; reg [(DATA_WIDTH-1):0] chan_data_0_r;
@ -149,7 +150,10 @@ module util_adc_pack (
reg [(DATA_WIDTH-1):0] chan_data_6_r; reg [(DATA_WIDTH-1):0] chan_data_6_r;
reg [(DATA_WIDTH-1):0] chan_data_7_r; reg [(DATA_WIDTH-1):0] chan_data_7_r;
wire chan_valid;
assign dsync = dvalid; assign dsync = dvalid;
assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
always @(posedge clk) always @(posedge clk)
begin begin
@ -166,98 +170,86 @@ module util_adc_pack (
end end
always @(posedge clk) always @(posedge clk)
begin
chan_valid <= chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
chan_data_0_r <= chan_data_0;
chan_data_1_r <= chan_data_1;
chan_data_2_r <= chan_data_2;
chan_data_3_r <= chan_data_3;
chan_data_4_r <= chan_data_4;
chan_data_5_r <= chan_data_5;
chan_data_6_r <= chan_data_6;
chan_data_7_r <= chan_data_7;
end
always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3, chan_valid)
begin begin
if(chan_valid == 1'b1) if(chan_valid == 1'b1)
begin begin
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) chan_data_0_r <= chan_data_0;
4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r; chan_data_1_r <= chan_data_1;
4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r; chan_data_2_r <= chan_data_2;
4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r; chan_data_3_r <= chan_data_3;
4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r; chan_data_4_r <= chan_data_4;
default: temp_data_0 [(DATA_WIDTH-1):0] = 0; chan_data_5_r <= chan_data_5;
endcase chan_data_6_r <= chan_data_6;
chan_data_7_r <= chan_data_7;
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r;
4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
endcase
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r;
4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
endcase
case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r;
default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
endcase
end
else
begin
temp_data_0 = 0;
end end
end end
always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7, chan_valid) always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 )
begin begin
if(chan_valid == 1'b1) casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
begin 4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r;
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) 4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r;
4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r; 4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r;
4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r; 4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r;
4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r; default: temp_data_0 [(DATA_WIDTH-1):0] = 0;
4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r; endcase
default: temp_data_1[(DATA_WIDTH-1):0] = 0;
endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r; 4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r;
4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; 4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; 4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; 4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; 4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; 4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0; default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
endcase endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r; 4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r;
4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; 4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; 4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; 4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
endcase endcase
case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r; 4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r;
default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
endcase endcase
end end
else
begin always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7)
temp_data_1 = 0; begin
end casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r;
4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r;
4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r;
4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r;
default: temp_data_1[(DATA_WIDTH-1):0] = 0;
endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r;
4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r;
4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
endcase
case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r;
default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
endcase
end end
always @(enable_cnt) always @(enable_cnt)