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axi_hdmi_rx: General clean up

main
Istvan Csomortani 2015-03-23 12:39:26 +02:00
parent c1c6787b91
commit 80c2a5a45d
6 changed files with 143 additions and 207 deletions
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94
library/axi_hdmi_rx/axi_hdmi_rx.v
View File

@ -44,12 +44,12 @@ module axi_hdmi_rx (
hdmi_clk,
hdmi_data,
// vdma interface
video_clk,
video_valid,
video_data,
video_overflow,
video_sync,
// dma interface
dma_clk,
dma_valid,
dma_data,
dma_ovf,
dma_sync,
// processor interface
@ -76,8 +76,7 @@ module axi_hdmi_rx (
// debug interface (chipscope)
hdmi_dbg_data,
hdmi_dbg_trigger);
hdmi_dbg_data);
// parameters
@ -90,11 +89,11 @@ module axi_hdmi_rx (
// vdma interface
output video_clk;
output video_valid;
output [63:0] video_data;
input video_overflow;
output video_sync;
output dma_clk;
output dma_valid;
output [63:0] dma_data;
input dma_ovf;
output dma_sync;
// processor interface
@ -118,10 +117,9 @@ module axi_hdmi_rx (
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug interface (chipscope)
// debug interface
output [61:0] hdmi_dbg_data;
output [ 7:0] hdmi_dbg_trigger;
reg [31:0] up_scratch = 'h0;
reg up_packed = 'd0;
@ -156,23 +154,21 @@ module axi_hdmi_rx (
wire [15:0] hdmi_vs_count_s;
wire hdmi_tpm_oos_s;
wire hdmi_oos_s;
wire hdmi_soos_hs_s;
wire hdmi_oos_hs_s;
wire hdmi_oos_vs_s;
wire hdmi_wr_s;
wire [64:0] hdmi_wdata_s;
wire up_hdmi_tpm_oos;
wire up_hdmi_oos;
wire up_hdmi_oos_hs;
wire up_hdmi_oos_vs;
wire hdmi_up_edge_sel;
wire [15:0] hdmi_up_hs_count;
wire [15:0] hdmi_up_vs_count;
wire hdmi_up_csc_bypass;
wire hdmi_up_tpg_enable;
wire hdmi_up_packed;
wire hdmi_rst;
wire hdmi_up_bgr;
wire hdmi_up_edge_sel_s;
wire [15:0] hdmi_up_hs_count_s;
wire [15:0] hdmi_up_vs_count_s;
wire hdmi_up_csc_bypass_s;
wire hdmi_up_tpg_enable_s;
wire hdmi_up_packed_s;
wire hdmi_rst_s;
wire hdmi_up_bgr_s;
up_axi i_up_axi (
.up_rstn(s_axi_aresetn),
@ -205,14 +201,14 @@ module axi_hdmi_rx (
up_hdmi_rx i_up_hdmi_rx (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_up_hs_count (hdmi_up_hs_count),
.hdmi_up_vs_count (hdmi_up_vs_count),
.hdmi_up_edge_sel (hdmi_up_edge_sel),
.hdmi_up_csc_bypass (hdmi_up_csc_bypass),
.hdmi_up_tpg_enable (hdmi_up_tpg_enable),
.hdmi_up_packed (hdmi_up_packed),
.hdmi_up_bgr (hdmi_up_bgr),
.hdmi_rst (hdmi_rst_s),
.hdmi_up_hs_count (hdmi_up_hs_count_s),
.hdmi_up_vs_count (hdmi_up_vs_count_s),
.hdmi_up_edge_sel (hdmi_up_edge_sel_s),
.hdmi_up_csc_bypass (hdmi_up_csc_bypass_s),
.hdmi_up_tpg_enable (hdmi_up_tpg_enable_s),
.hdmi_up_packed (hdmi_up_packed_s),
.hdmi_up_bgr (hdmi_up_bgr_s),
.hdmi_hs_mismatch (hdmi_hs_count_mismatch_s),
.hdmi_hs (hdmi_hs_count_s),
.hdmi_vs_mismatch (hdmi_vs_count_mismatch_s),
@ -220,7 +216,7 @@ module axi_hdmi_rx (
.hdmi_oos_hs (hdmi_oos_hs_s),
.hdmi_oos_vs (hdmi_oos_vs_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.video_overflow (video_overflow),
.dma_ovf (dma_ovf),
.up_clk (s_axi_aclk),
.up_rstn (s_axi_aresetn),
.up_rdata (up_rdata_s),
@ -232,16 +228,16 @@ module axi_hdmi_rx (
.up_wack (up_wack_s),
.up_rack (up_rack_s));
assign video_clk = hdmi_clk;
assign video_data = hdmi_wdata_s[63:0];
assign video_sync = hdmi_wdata_s[64];
assign video_valid = hdmi_wr_s;
assign dma_clk = hdmi_clk;
assign dma_data = hdmi_wdata_s[63:0];
assign dma_sync = hdmi_wdata_s[64];
assign dma_valid = hdmi_wr_s;
// hdmi interface
axi_hdmi_rx_core i_hdmi_rx_core (
.hdmi_clk(hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_rst (hdmi_rst_s),
.hdmi_data(hdmi_data),
.hdmi_hs_count_mismatch(hdmi_hs_count_mismatch_s),
.hdmi_hs_count_update(hdmi_hs_count_update),
@ -254,15 +250,13 @@ module axi_hdmi_rx (
.hdmi_oos_vs(hdmi_oos_vs_s),
.hdmi_wr(hdmi_wr_s),
.hdmi_wdata(hdmi_wdata_s),
.hdmi_up_edge_sel(hdmi_up_edge_sel),
.hdmi_up_hs_count(hdmi_up_hs_count),
.hdmi_up_vs_count(hdmi_up_vs_count),
.hdmi_up_csc_bypass(hdmi_up_csc_bypass),
.hdmi_up_tpg_enable(hdmi_up_tpg_enable),
.hdmi_up_packed(hdmi_up_packed),
.hdmi_up_bgr(hdmi_up_bgr),
.debug_data(hdmi_dbg_data),
.debug_trigger(hdmi_dbg_trigger)
);
.hdmi_up_edge_sel(hdmi_up_edge_sel_s),
.hdmi_up_hs_count(hdmi_up_hs_count_s),
.hdmi_up_vs_count(hdmi_up_vs_count_s),
.hdmi_up_csc_bypass(hdmi_up_csc_bypass_s),
.hdmi_up_tpg_enable(hdmi_up_tpg_enable_s),
.hdmi_up_packed(hdmi_up_packed_s),
.hdmi_up_bgr(hdmi_up_bgr_s),
.debug_data(hdmi_dbg_data));
endmodule

4
library/axi_hdmi_rx/axi_hdmi_rx_constr.xdc
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@ -1,4 +1,4 @@
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports hdmi_clk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports -regexp .*_clk$]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports video_clk]]

125
library/axi_hdmi_rx/axi_hdmi_rx_core.v
View File

@ -66,10 +66,9 @@ module axi_hdmi_rx_core (
hdmi_up_packed,
hdmi_up_bgr,
// debug interface (chipscope)
// debug interface
debug_data,
debug_trigger);
debug_data);
// hdmi interface
@ -101,7 +100,6 @@ module axi_hdmi_rx_core (
// debug interface (chipscope)
output [61:0] debug_data;
output [ 7:0] debug_trigger;
reg hdmi_wr = 'd0;
reg [64:0] hdmi_wdata = 'd0;
@ -138,6 +136,25 @@ module axi_hdmi_rx_core (
reg [15:0] hdmi_data_neg = 'd0;
reg [ 2:0] hdmi_wr_count = 'd0;
reg [15:0] data_d = 'd0;
reg [15:0] data_2d = 'd0;
reg [15:0] data_3d = 'd0;
reg [15:0] data_4d = 'd0;
reg hs_de_rcv_d = 'd0;
reg hs_de_rcv_2d = 'd0;
reg hs_de_rcv_3d = 'd0;
reg hs_de_rcv_4d = 'd0;
reg vs_de_rcv_d = 'd0;
reg vs_de_rcv_2d = 'd0;
reg vs_de_rcv_3d = 'd0;
reg vs_de_rcv_4d = 'd0;
reg hs_de_rcv = 'd0;
reg vs_de_rcv = 'd0;
reg [ 1:0] preamble_cnt = 'd0;
reg [15:0] hdmi_data_de;
reg hdmi_hs_de;
reg hdmi_vs_de;
wire hdmi_tpm_mismatch_s;
wire [15:0] hdmi_tpm_data_s;
wire hdmi_sof_s;
@ -149,9 +166,9 @@ module axi_hdmi_rx_core (
wire ss_fs_s;
wire ss_de_s;
wire [23:0] ss_data_s;
wire [15:0] hdmi_data_de;
wire hdmi_hs_de;
wire hdmi_vs_de;
wire [15:0] hdmi_data_de_s;
wire hdmi_hs_de_s;
wire hdmi_vs_de_s;
// debug signals
@ -164,19 +181,11 @@ module axi_hdmi_rx_core (
assign debug_data[40:40] = hdmi_hs_count_mismatch;
assign debug_data[39:39] = hdmi_vs_count_mismatch;
assign debug_data[38:38] = hdmi_enable;
assign debug_data[37:37] = hdmi_vs_de;
assign debug_data[36:36] = hdmi_hs_de;
assign debug_data[35:20] = hdmi_data_de;
assign debug_data[37:37] = hdmi_vs_de_s;
assign debug_data[36:36] = hdmi_hs_de_s;
assign debug_data[35:20] = hdmi_data_de_s;
assign debug_data[15: 0] = hdmi_data_p;
assign debug_trigger[7] = hdmi_tpm_mismatch_s;
assign debug_trigger[6] = hdmi_tpm_oos;
assign debug_trigger[5] = hdmi_enable;
assign debug_trigger[4] = hdmi_hs_de;
assign debug_trigger[3] = hdmi_vs_de;
assign debug_trigger[2] = hdmi_sof;
always @(posedge hdmi_clk) begin
if (hdmi_de_444_d == 1'b1) begin
hdmi_wr_count <= hdmi_wr_count + 1'b1;
@ -222,12 +231,12 @@ module axi_hdmi_rx_core (
end
endcase
end
end
end
if (hdmi_fs_444)
hdmi_wdata[64:64] <= 1'b1;
else if (hdmi_wr)
hdmi_wdata[64:64] <= 1'b0;
if (hdmi_fs_444)
hdmi_wdata[64:64] <= 1'b1;
else if (hdmi_wr)
hdmi_wdata[64:64] <= 1'b0;
end
// TPM on 422 data (the data must be passed through the cable as it is transmitted
@ -247,15 +256,14 @@ end
// fs, enable and data on 422 and 444 domains
always @(posedge hdmi_clk) begin
hdmi_fs_422 <= hdmi_sof & hdmi_enable;
hdmi_de_422 <= hdmi_hs_de & hdmi_vs_de & hdmi_enable;
hdmi_data_422 <= hdmi_data_de;
hdmi_fs_444_d <= hdmi_fs_444;
hdmi_de_444_d <= hdmi_de_444;
hdmi_data_444_d <= hdmi_data_444;
hdmi_data_444_2d <= hdmi_data_444_d;
hdmi_data_444_3d <= hdmi_data_444_2d;
hdmi_fs_422 <= hdmi_sof & hdmi_enable;
hdmi_de_422 <= hdmi_hs_de & hdmi_vs_de & hdmi_enable;
hdmi_data_422 <= hdmi_data_de_s;
hdmi_fs_444_d <= hdmi_fs_444;
hdmi_de_444_d <= hdmi_de_444;
hdmi_data_444_d <= hdmi_data_444;
hdmi_data_444_2d <= hdmi_data_444_d;
hdmi_data_444_3d <= hdmi_data_444_2d;
end
// Select output data depending on the control setting
@ -338,13 +346,52 @@ end
hdmi_data_neg <= hdmi_data;
end
embedded_sync_decoder es_decoder (
.clk (hdmi_clk),
.data_in (hdmi_data_p),
.hs_de (hdmi_hs_de),
.vs_de (hdmi_vs_de),
.data_out (hdmi_data_de)
);
// delay to get rid of eav's 4 bytes
always @(posedge hdmi_clk) begin
data_d <= hdmi_data_p;
data_2d <= data_d;
data_3d <= data_2d;
data_4d <= data_3d;
hdmi_data_de <= data_4d;
hs_de_rcv_d <= hs_de_rcv;
vs_de_rcv_d <= vs_de_rcv;
hs_de_rcv_2d <= hs_de_rcv_d;
vs_de_rcv_2d <= vs_de_rcv_d;
hs_de_rcv_3d <= hs_de_rcv_2d;
vs_de_rcv_3d <= vs_de_rcv_2d;
hs_de_rcv_4d <= hs_de_rcv_3d;
vs_de_rcv_4d <= vs_de_rcv_3d;
hdmi_hs_de <= hs_de_rcv & hs_de_rcv_4d;
hdmi_vs_de <= vs_de_rcv & vs_de_rcv_4d;
end
assign hdmi_data_de_s = hdmi_data_de;
assign hdmi_hs_de_s = hdmi_hs_de;
assign hdmi_vs_de_s = hdmi_vs_de;
// check for sav and eav and generate the corresponding enables
always @(posedge hdmi_clk) begin
if ((hdmi_data_p == 16'hffff) || (hdmi_data_p == 16'h0000)) begin
preamble_cnt <= preamble_cnt + 1'b1;
end else begin
preamble_cnt <= 'd0;
end
if (preamble_cnt == 3'h3) begin
if ((hdmi_data_p == 16'hb6b6) || (hdmi_data_p == 16'h9d9d)) begin
hs_de_rcv <= 1'b0;
vs_de_rcv <= ~hdmi_data_p[13];
end else if ((hdmi_data_p == 16'habab) || (hdmi_data_p == 16'h8080)) begin
hs_de_rcv <= 1'b1;
vs_de_rcv <= ~hdmi_data_p[13];
end
end
end
// super sampling, 422 to 444

3
library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
View File

@ -17,8 +17,7 @@ adi_ip_files axi_hdmi_rx [list \
"$ad_hdl_dir/library/common/ad_ss_422to444.v" \
"$ad_hdl_dir/library/common/ad_csc_CrYCb2RGB.v" \
"axi_hdmi_rx.v" \
"axi_hdmi_rx_core.v" \
"embedded_sync_decoder.v" ]
"axi_hdmi_rx_core.v" ]
adi_ip_properties axi_hdmi_rx
adi_ip_constraints axi_hdmi_rx [list \

104
library/axi_hdmi_rx/embedded_sync_decoder.v
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@ -1,104 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011-2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module embedded_sync_decoder(
input clk,
input [15:0] data_in,
output reg hs_de,
output reg vs_de,
output reg [15:0] data_out
);
reg [15:0] data_d = 'd0;
reg hs_de_rcv_d = 'd0;
reg vs_de_rcv_d = 'd0;
reg [15:0] data_2d = 'd0;
reg hs_de_rcv_2d = 'd0;
reg vs_de_rcv_2d = 'd0;
reg [15:0] data_3d = 'd0;
reg hs_de_rcv_3d = 'd0;
reg vs_de_rcv_3d = 'd0;
reg [15:0] data_4d = 'd0;
reg hs_de_rcv_4d = 'd0;
reg vs_de_rcv_4d = 'd0;
reg hs_de_rcv = 'd0;
reg vs_de_rcv = 'd0;
// delay to get rid of eav's 4 bytes
always @(posedge clk) begin
data_d <= data_in;
data_2d <= data_d;
data_3d <= data_2d;
data_4d <= data_3d;
data_out <= data_4d;
hs_de_rcv_d <= hs_de_rcv;
vs_de_rcv_d <= vs_de_rcv;
hs_de_rcv_2d <= hs_de_rcv_d;
vs_de_rcv_2d <= vs_de_rcv_d;
hs_de_rcv_3d <= hs_de_rcv_2d;
vs_de_rcv_3d <= vs_de_rcv_2d;
hs_de_rcv_4d <= hs_de_rcv_3d;
vs_de_rcv_4d <= vs_de_rcv_3d;
hs_de <= hs_de_rcv & hs_de_rcv_4d;
vs_de <= vs_de_rcv & vs_de_rcv_4d;
end
reg [1:0] preamble_cnt = 'd0;
// check for sav and eav and generate the corresponding enables
always @(posedge clk) begin
if ((data_in == 16'hffff) || (data_in == 16'h0000)) begin
preamble_cnt <= preamble_cnt + 1'b1;
end else begin
preamble_cnt <= 'd0;
end
if (preamble_cnt == 3'h3) begin
if ((data_in == 16'hb6b6) || (data_in == 16'h9d9d)) begin
hs_de_rcv <= 1'b0;
vs_de_rcv <= ~data_in[13];
end else if ((data_in == 16'habab) || (data_in == 16'h8080)) begin
hs_de_rcv <= 1'b1;
vs_de_rcv <= ~data_in[13];
end
end
end
endmodule

20
library/common/up_hdmi_rx.v
View File

@ -60,9 +60,9 @@ module up_hdmi_rx (
hdmi_oos_hs,
hdmi_oos_vs,
// vdma interface
// dma fifo overflow
video_overflow,
dma_ovf,
// bus interface
@ -99,7 +99,7 @@ module up_hdmi_rx (
// vdma interface
input video_overflow;
input dma_ovf;
input hdmi_hs_mismatch;
input [15:0] hdmi_hs;
input hdmi_vs_mismatch;
@ -136,7 +136,7 @@ module up_hdmi_rx (
reg [15:0] up_hs_count = 'd0;
reg [ 3:0] up_hdmi_status_hold = 'd0;
reg up_status = 'd0;
reg up_vdma_ovf_hold = 'd0;
reg up_dma_ovf_hold = 'd0;
reg up_hdmi_tpm_oos_hold = 'd0;
// internal signals
@ -153,7 +153,7 @@ module up_hdmi_rx (
wire [3:0] up_hdmi_status = {up_hdmi_oos_vs, up_hdmi_oos_hs, up_hdmi_vs_mismatch, up_hdmi_hs_mismatch};
wire up_vdma_ovf;
wire up_dma_ovf;
// decode block select
@ -199,9 +199,9 @@ module up_hdmi_rx (
up_hs_count <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_vdma_ovf_hold <= (up_vdma_ovf_hold & ~up_wdata[0]) | up_vdma_ovf;
up_dma_ovf_hold <= (up_dma_ovf_hold & ~up_wdata[0]) | up_dma_ovf;
end else begin
up_vdma_ovf_hold <= up_vdma_ovf_hold | up_vdma_ovf;
up_dma_ovf_hold <= up_dma_ovf_hold | up_dma_ovf;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_hdmi_tpm_oos_hold <= (up_hdmi_tpm_oos_hold & ~up_wdata[0]) | up_hdmi_tpm_oos;
@ -232,7 +232,7 @@ module up_hdmi_rx (
12'h010: up_rdata <= {31'h0, up_resetn};
12'h011: up_rdata <= {29'h0, up_bgr, up_packed, up_csc_bypass};
12'h012: up_rdata <= {31'h0, up_tpg_enable};
12'h018: up_rdata <= {30'h0, up_vdma_ovf_hold, 1'b0};
12'h018: up_rdata <= {30'h0, up_dma_ovf_hold, 1'b0};
12'h019: up_rdata <= {30'h0, up_hdmi_tpm_oos_hold, 1'b0};
12'h020: up_rdata <= {28'h0, up_hdmi_status_hold};
12'h100: up_rdata <= {up_vs_count, up_hs_count};
@ -320,10 +320,10 @@ module up_hdmi_rx (
) i_vdma_xfer_status (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(up_vdma_ovf),
.up_data_status(up_dma_ovf),
.d_rst(hdmi_rst),
.d_clk(hdmi_clk),
.d_data_status(video_overflow));
.d_data_status(dma_ovf));
endmodule