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upack/cpack- qsys ip

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Rejeesh Kutty 2016-05-18 13:22:04 -04:00
parent a262eb7ab3
commit 7fdaee186c
2 changed files with 9 additions and 8 deletions
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16
library/util_cpack/util_cpack_hw.tcl
View File

@ -51,7 +51,7 @@ add_interface_port adc_ch_0 adc_valid_0 valid Input 1
add_interface_port adc_ch_0 adc_data_0 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset if_adc_rst
set_interface_property adc_ch_0 associatedReset none
proc p_util_cpack {} {
@ -63,7 +63,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_1 adc_data_1 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset if_adc_rst
set_interface_property adc_ch_1 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
@ -74,7 +74,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_2 adc_data_2 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset if_adc_rst
set_interface_property adc_ch_2 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
@ -85,7 +85,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_3 adc_data_3 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset if_adc_rst
set_interface_property adc_ch_3 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
@ -96,7 +96,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_4 adc_data_4 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_4 associatedClock if_adc_clk
set_interface_property adc_ch_4 associatedReset if_adc_rst
set_interface_property adc_ch_4 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
@ -107,7 +107,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_5 adc_data_5 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_5 associatedClock if_adc_clk
set_interface_property adc_ch_5 associatedReset if_adc_rst
set_interface_property adc_ch_5 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
@ -118,7 +118,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_6 adc_data_6 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_6 associatedClock if_adc_clk
set_interface_property adc_ch_6 associatedReset if_adc_rst
set_interface_property adc_ch_6 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
@ -129,7 +129,7 @@ proc p_util_cpack {} {
add_interface_port adc_ch_7 adc_data_7 data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_7 associatedClock if_adc_clk
set_interface_property adc_ch_7 associatedReset if_adc_rst
set_interface_property adc_ch_7 associatedReset none
}
}

1
library/util_upack/util_upack_hw.tcl
View File

@ -53,6 +53,7 @@ add_interface_port dac_ch_0 dac_valid_0 valid Input 1
add_interface_port dac_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH
set_interface_property dac_ch_0 associatedClock if_dac_clk
set_interface_property dac_ch_0 associatedReset none
proc p_util_upack {} {