fmcomms11- xcvr updates
Rejeesh Kutty
parent
ad16aec101
commit
7fd9280cbf
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@ -24,13 +24,13 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9162/axi_ad9162.xpr
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M_DEPS += ../../../library/axi_ad9625/axi_ad9625.xpr
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M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
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M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
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M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
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M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
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M_VIVADO := vivado -mode batch -source
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@ -62,13 +62,13 @@ clean-all:clean
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make -C ../../../library/axi_ad9162 clean
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make -C ../../../library/axi_ad9625 clean
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make -C ../../../library/xilinx/axi_adcfifo clean
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make -C ../../../library/xilinx/axi_adxcvr clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/xilinx/util_adxcvr clean
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make -C ../../../library/util_dacfifo clean
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make -C ../../../library/util_jesd_gt clean
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fmcomms11_zc706.sdk/system_top.hdf: $(M_DEPS)
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@ -80,13 +80,13 @@ lib:
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make -C ../../../library/axi_ad9162
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make -C ../../../library/axi_ad9625
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make -C ../../../library/xilinx/axi_adcfifo
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make -C ../../../library/xilinx/axi_adxcvr
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/xilinx/util_adxcvr
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make -C ../../../library/util_dacfifo
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make -C ../../../library/util_jesd_gt
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####################################################################################
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####################################################################################
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@ -67,6 +67,9 @@ set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_i
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create_clock -name tx_ref_clk -period 6.40 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 6.40 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_fmcomms11_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
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@ -279,10 +279,25 @@ module system_top (
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.rx_data_n (rx_data_n),
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.rx_data_p (rx_data_p),
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_data_4_n (rx_data_n[4]),
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.rx_data_4_p (rx_data_p[4]),
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.rx_data_5_n (rx_data_n[5]),
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.rx_data_5_p (rx_data_p[5]),
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.rx_data_6_n (rx_data_n[6]),
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.rx_data_6_p (rx_data_p[6]),
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.rx_data_7_n (rx_data_n[7]),
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.rx_data_7_p (rx_data_p[7]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (sysref),
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.spdif (spdif),
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.spi0_clk_i (spi0_clk),
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.spi0_clk_o (spi0_clk),
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@ -305,11 +320,25 @@ module system_top (
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.sys_clk_clk_n (sys_clk_n),
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.sys_clk_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.sysref (sysref),
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.tx_data_n (tx_data_n),
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.tx_data_p (tx_data_p),
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.tx_ref_clk (tx_ref_clk),
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.tx_sync (tx_sync));
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.tx_data_0_n (tx_data_n[0]),
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.tx_data_0_p (tx_data_p[0]),
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.tx_data_1_n (tx_data_n[1]),
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.tx_data_1_p (tx_data_p[1]),
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.tx_data_2_n (tx_data_n[2]),
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.tx_data_2_p (tx_data_p[2]),
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.tx_data_3_n (tx_data_n[3]),
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.tx_data_3_p (tx_data_p[3]),
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.tx_data_4_n (tx_data_n[4]),
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.tx_data_4_p (tx_data_p[4]),
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.tx_data_5_n (tx_data_n[5]),
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.tx_data_5_p (tx_data_p[5]),
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.tx_data_6_n (tx_data_n[6]),
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.tx_data_6_p (tx_data_p[6]),
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.tx_data_7_n (tx_data_n[7]),
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.tx_data_7_p (tx_data_p[7]),
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.tx_ref_clk_0 (tx_ref_clk),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (sysref));
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endmodule
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