Project scripts: Initial check in of adi_board.tcl
The script contains integration tcl processes.main
Istvan Csomortani
parent
f9a67371c0
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7f4f200fce
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#----------------------------------------------------------------------------
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# Internal processes
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#----------------------------------------------------------------------------
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# ensure that in case of a port number less than 10, the number format to be 0X
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proc set_num {number} {
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if { $number < 10} {
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return "0${number}"
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} else {
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return $number
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}
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}
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# search the first free HP port in case of a Zynq device
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proc free_hp_port {} {
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set hp_port_num 0
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set hp_port 1
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while(hp_port) {
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set hp_port_num [expr hp_port_num + 1]
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set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" [get_bd_cells sys_ps7]]
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}
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return $hp_port_num
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}
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#----------------------------------------------------------------------------
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# Integration processes
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#----------------------------------------------------------------------------
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# For AXI_LITE interconnect connections
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proc adi_interconnect_lite { peripheral_name peripheral_address } {
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set peripheral_port_name "s_axi"
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set peripheral_base_name "axi_lite"
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set peripheral_address_range 0x00010000
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set interconnect_bd [get_bd_cells axi_cpu_interconnect]
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# increment the number of the master ports of the interconnect
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set number_of_master [get_property CONFIG.NUM_MI $interconnect_bd]
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set number_of_master [expr $number_of_master + 1]
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set_property CONFIG.NUM_MI $number_of_master $interconnect_bd
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# check processor type, connect system clock and reset to the peripheral
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if { [get_bd_cells sys_ps7] != {} } {
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# sys_proc is a zynq
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set sys_proc [get_bd_cells sys_ps7]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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connect_bd_net -net sys_100m_clk [get_bd_pins "${peripheral_name}/s_axi_aclk"]
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connect_bd_net -net sys_100m_resetn [get_bd_pins "${peripheral_name}/s_axi_aresetn"]
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} else {
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# sys_proc is a micorblaze
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set sys_proc [get_bd_cells sys_mb]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_100m_clk [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn_intc [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
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# connect clk and reset for the peripheral port
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connect_bd_net -net sys_100m_clk [get_bd_pins "${peripheral_name}/s_axi_aclk"]
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connect_bd_net -net sys_100m_resetn [get_bd_pins "${peripheral_name}/s_axi_aresetn"]
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}
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# if peripheral is a Xilinx core
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if { [regexp "^analog*" [get_property VLNV [get_bd_cells $peripheral_name]]] == 0 } {
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set peripheral_base_name "Reg"
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if { [regexp "^xilinx.*spi*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
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set peripheral_port_name "axi_lite"
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} elseif { [regexp "^xilinx.*dma*" [get_property VLNV [get_bd_cells $peripheral_name]]] } {
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set peripheral_port_name "S_AXI_LITE"
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} else {
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set peripheral_port_name "s_axi"
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}
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}
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# make the port connection
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connect_bd_intf_net -intf_net "axi_cpu_interconnect_m${number_of_master}" [get_bd_intf_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_AXI"] [get_bd_intf_pins "${peripheral_name}/${peripheral_port_name}"]
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# define address space for the peripheral
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create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address $::sys_addr_cntrl_space [get_bd_addr_segs "${peripheral_name}/${peripheral_port_name}/${peripheral_base_name}"] "SEG_data_${peripheral_name}_axi_lite"
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}
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# Set up the SPI core
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proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
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# define SPI ports
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set spi_csn_i [create_bd_port -dir I -from [expr spi_ss_width - 1] -to 0 spi_csn_i]
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set spi_csn_o [create_bd_port -dir O -from [expr spi_ss_width - 1] -to 0 spi_csn_o]
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set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
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set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
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set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
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set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
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set spi_miso_i [create_bd_port -dir I spi_miso_i]
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# check processor type, connect system clock and reset to the peripheral
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if { [get_bd_cells sys_ps7] != {} } {
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# add SPI interface to ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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# connect the interface to the ports
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_sclk_i [get_bd_ports spi_sclk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_sclk_o [get_bd_ports spi_sclk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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} else {
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# instanciate AXI_SPI core
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set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name
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set_property -dict [list CONFIG.C_NUM_SS_BITS {$spi_ss_width}] $spi_name
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set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
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set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
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# spi external ports
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins "${spi_name}/ss_i"]
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins "${spi_name}/ss_o"]
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connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins "${spi_name}/sck_o"]
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connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins "${spi_name}/sck_i"]
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connect_bd_net -net spi_mosi_o [get_bd_pins spi_sdo_o] [get_bd_pins "${spi_name}/io0_o"]
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connect_bd_net -net spi_mosi_i [get_bd_pins spi_sdo_i] [get_bd_pins "${spi_name}/io0_i"]
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connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins "${spi_name}/io1_i"]
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create_bd_addr_seg -range 0x00010000 -offset $spi_base_addr $::sys_addr_cntrl_space [get_bd_addr_segs "${spi_name}/axi_lite/Reg"] "SEG_data_${spi_name}"
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}
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#TODO: - Interrupts
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#
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}
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# For AXI interconnect connections between dma and 'ddr controller'/HP port
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proc adi_dma_interconnect { dma_name port_name} {
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# check processor type, connect system clock and reset to the peripheral
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if { [get_bd_cells sys_ps7] != {} } {
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set hp_port [free_hp_port]
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set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] $sys_ps7
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set axi_dma_interconnect_($hp_port) [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_($hp_port)]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_($hp_port)
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# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ddr_interconnect/M00_ACLK] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
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connect_bd_net -net sys_100m_clk [get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
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connect_bd_intf_net -intf_net axi_ddr_interconnect_m00_axi [get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_200m_clk [get_bd_pins "${axi_dma_interconnect_($hp_port)}/S00_ACLK"] [get_bd_pins $clk]
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connect_bd_net -net sys_100m_resetn_intc [get_bd_pins "$axi_dma_interconnect_($hp_port)/S00_ARESETN"] [get_bd_pins $reset_i]
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# connect clk and reset for the peripheral port
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puts "${dma_name}/${peripheral_port}_aclk"
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connect_bd_net -net sys_200m_clk [get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
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connect_bd_net -net sys_200m_resetn [get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
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# Connect the interconnect to the dma
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connect_bd_intf_net -intf_net ${dma_name}_interconnect_s00_axi [get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] [get_bd_intf_pins "${dma_name}/${port_name}"]
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# Definte address space
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create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 [get_bd_addr_spaces "${dma_name}/${port_name}"] [get_bd_addr_segs "sys_ps7/S_AXI_HP${hp_port}/HP${hp_port}_DDR_LOWOCM"] "SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
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} else {
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set axi_ddr_interconnect [get_bd_cells axi_ddr_interconnect]
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# increment the number of the master ports of the interconnect
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set number_of_slave [get_property CONFIG.NUM_SI $axi_ddr_interconnect]
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set number_of_slave [expr $number_of_slave + 1]
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set_property CONFIG.NUM_SI $number_of_slave $axi_ddr_interconnect
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# sys_proc is a micorblaze
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set sys_ddr [get_bd_cells axi_ddr_cntrl_1]
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set clk "/axi_ddr_cntrl_1/ui_clk"
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set reset "/proc_sys_reset_1/peripheral_aresetn"
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set reset_i "/proc_sys_reset_1/interconnect_aresetn"
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# connect clk and reset for the interconnect
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connect_bd_net -net sys_200m_clk [get_bd_pins "${axi_ddr_interconnect}/S0[expr $number_of_slave-1]_ACLK"] [get_bd_pins $clk]
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connect_bd_net -net sys_100m_resetn_intc [get_bd_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_ARESETN"] [get_bd_pins $reset_i]
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# connect clk and reset for the peripheral port
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puts "${dma_name}/${peripheral_port}_aclk"
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connect_bd_net -net sys_200m_clk [get_bd_pins "${dma_name}/${peripheral_port}_aclk"]
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connect_bd_net -net sys_200m_resetn [get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
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}
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# make the port connection
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connect_bd_intf_net -intf_net "axi_ddr_interconnect_s${number_of_slave}" [get_bd_intf_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_AXI"] [get_bd_intf_pins "${dma_name}/${peripheral_port}"]
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# define address space for the peripheral
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create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address [get_bd_addr_spaces "${dma_name}/${peripheral_port}"] [get_bd_addr_segs "${sys_ddr}/memmap/memaddr"] "SEG_data_${dma_name}_2_ddr"
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}
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