diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v new file mode 100644 index 000000000..d0459cdd5 --- /dev/null +++ b/library/axi_ad9144/axi_ad9144.v @@ -0,0 +1,262 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144 ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dma interface + + dac_clk, + dac_drd, + dac_ddata, + dac_dovf, + dac_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rdata, + s_axi_rresp, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter PCORE_QUAD_DUAL_N = 1; + parameter PCORE_DAC_DP_DISABLE = 0; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_BASEADDR = 32'hffffffff; + parameter C_HIGHADDR = 32'h00000000; + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [(128*PCORE_QUAD_DUAL_N)+127:0] tx_data; + + // dma interface + + output dac_clk; + output dac_drd; + input [(128*PCORE_QUAD_DUAL_N)+127:0] dac_ddata; + input dac_dovf; + input dac_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [ 31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [ 31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [ 31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 31:0] s_axi_rdata; + output [ 1:0] s_axi_rresp; + input s_axi_rready; + + // internal clocks and resets + + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [255:0] tx_data_s; + wire [255:0] dac_ddata_s; + wire [ 15:0] dac_data_i0_0_s; + wire [ 15:0] dac_data_i0_1_s; + wire [ 15:0] dac_data_i0_2_s; + wire [ 15:0] dac_data_i0_3_s; + wire [ 15:0] dac_data_q0_0_s; + wire [ 15:0] dac_data_q0_1_s; + wire [ 15:0] dac_data_q0_2_s; + wire [ 15:0] dac_data_q0_3_s; + wire [ 15:0] dac_data_i1_0_s; + wire [ 15:0] dac_data_i1_1_s; + wire [ 15:0] dac_data_i1_2_s; + wire [ 15:0] dac_data_i1_3_s; + wire [ 15:0] dac_data_q1_0_s; + wire [ 15:0] dac_data_q1_1_s; + wire [ 15:0] dac_data_q1_2_s; + wire [ 15:0] dac_data_q1_3_s; + wire up_sel_s; + wire up_wr_s; + wire [ 13:0] up_addr_s; + wire [ 31:0] up_wdata_s; + wire [ 31:0] up_rdata_s; + wire up_ack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // dual/quad cores + + assign tx_data = (PCORE_QUAD_DUAL_N == 1) ? tx_data_s : tx_data_s[127:0]; + assign dac_ddata_s = (PCORE_QUAD_DUAL_N == 1) ? dac_ddata : {32'd0, dac_ddata[127:96], + 32'd0, dac_ddata[95:64], 32'd0, dac_ddata[63:32], 32'd0, dac_ddata[31:0]}; + + // device interface + + axi_ad9144_if i_if ( + .tx_clk (tx_clk), + .tx_data (tx_data_s), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_i0_0 (dac_data_i0_0_s), + .dac_data_i0_1 (dac_data_i0_1_s), + .dac_data_i0_2 (dac_data_i0_2_s), + .dac_data_i0_3 (dac_data_i0_3_s), + .dac_data_q0_0 (dac_data_q0_0_s), + .dac_data_q0_1 (dac_data_q0_1_s), + .dac_data_q0_2 (dac_data_q0_2_s), + .dac_data_q0_3 (dac_data_q0_3_s), + .dac_data_i1_0 (dac_data_i1_0_s), + .dac_data_i1_1 (dac_data_i1_1_s), + .dac_data_i1_2 (dac_data_i1_2_s), + .dac_data_i1_3 (dac_data_i1_3_s), + .dac_data_q1_0 (dac_data_q1_0_s), + .dac_data_q1_1 (dac_data_q1_1_s), + .dac_data_q1_2 (dac_data_q1_2_s), + .dac_data_q1_3 (dac_data_q1_3_s)); + + // core + + axi_ad9144_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_i0_0 (dac_data_i0_0_s), + .dac_data_i0_1 (dac_data_i0_1_s), + .dac_data_i0_2 (dac_data_i0_2_s), + .dac_data_i0_3 (dac_data_i0_3_s), + .dac_data_q0_0 (dac_data_q0_0_s), + .dac_data_q0_1 (dac_data_q0_1_s), + .dac_data_q0_2 (dac_data_q0_2_s), + .dac_data_q0_3 (dac_data_q0_3_s), + .dac_data_i1_0 (dac_data_i1_0_s), + .dac_data_i1_1 (dac_data_i1_1_s), + .dac_data_i1_2 (dac_data_i1_2_s), + .dac_data_i1_3 (dac_data_i1_3_s), + .dac_data_q1_0 (dac_data_q1_0_s), + .dac_data_q1_1 (dac_data_q1_1_s), + .dac_data_q1_2 (dac_data_q1_2_s), + .dac_data_q1_3 (dac_data_q1_3_s), + .dac_drd (dac_drd), + .dac_ddata (dac_ddata_s), + .dac_dovf (dac_dovf), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_ack (up_ack_s)); + + // up bus interface + + up_axi #( + .PCORE_BASEADDR (C_BASEADDR), + .PCORE_HIGHADDR (C_HIGHADDR)) + i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_ack (up_ack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9144/axi_ad9144_channel.v b/library/axi_ad9144/axi_ad9144_channel.v new file mode 100644 index 000000000..6014291ad --- /dev/null +++ b/library/axi_ad9144/axi_ad9144_channel.v @@ -0,0 +1,174 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144_channel ( + + // dac interface + + dac_clk, + dac_rst, + dac_dds_data_0, + dac_dds_data_1, + dac_dds_data_2, + dac_dds_data_3, + + // processor interface + + dac_dds_enable, + dac_dds_format, + + // bus interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter CHID = 32'h0; + parameter DP_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + output [15:0] dac_dds_data_0; + output [15:0] dac_dds_data_1; + output [15:0] dac_dds_data_2; + output [15:0] dac_dds_data_3; + + // processor interface + + input dac_dds_enable; + input dac_dds_format; + + // bus interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire [ 3:0] dac_dds_sel_s; + wire [15:0] dac_dds_patt_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_patt_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_dds_scale_2_s; + + // single channel dds + + axi_ad9144_dds #(.DP_DISABLE(DP_DISABLE)) i_dds ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_data_0 (dac_dds_data_0), + .dac_dds_data_1 (dac_dds_data_1), + .dac_dds_data_2 (dac_dds_data_2), + .dac_dds_data_3 (dac_dds_data_3), + .dac_dds_enable (dac_dds_enable), + .dac_dds_format (dac_dds_format), + .dac_dds_sel (dac_dds_sel_s), + .dac_dds_patt_1 (dac_dds_patt_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_patt_2 (dac_dds_patt_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_dds_scale_2 (dac_dds_scale_2_s)); + + // single channel processor + + up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_dds_patt_1 (dac_dds_patt_1_s), + .dac_dds_patt_2 (dac_dds_patt_2_s), + .dac_dds_sel (dac_dds_sel_s), + .dac_lb_enb (), + .dac_pn_enb (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v new file mode 100644 index 000000000..921663dbc --- /dev/null +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -0,0 +1,374 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144_core ( + + // dac interface + + dac_clk, + dac_rst, + dac_data_i0_0, + dac_data_i0_1, + dac_data_i0_2, + dac_data_i0_3, + dac_data_q0_0, + dac_data_q0_1, + dac_data_q0_2, + dac_data_q0_3, + dac_data_i1_0, + dac_data_i1_1, + dac_data_i1_2, + dac_data_i1_3, + dac_data_q1_0, + dac_data_q1_1, + dac_data_q1_2, + dac_data_q1_3, + + // dma interface + + dac_drd, + dac_ddata, + dac_dovf, + dac_dunf, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter PCORE_ID = 0; + parameter DP_DISABLE = 0; + + // dac interface + + input dac_clk; + output dac_rst; + output [15:0] dac_data_i0_0; + output [15:0] dac_data_i0_1; + output [15:0] dac_data_i0_2; + output [15:0] dac_data_i0_3; + output [15:0] dac_data_q0_0; + output [15:0] dac_data_q0_1; + output [15:0] dac_data_q0_2; + output [15:0] dac_data_q0_3; + output [15:0] dac_data_i1_0; + output [15:0] dac_data_i1_1; + output [15:0] dac_data_i1_2; + output [15:0] dac_data_i1_3; + output [15:0] dac_data_q1_0; + output [15:0] dac_data_q1_1; + output [15:0] dac_data_q1_2; + output [15:0] dac_data_q1_3; + + // dma interface + + output dac_drd; + input [255:0] dac_ddata; + input dac_dovf; + input dac_dunf; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal registers + + reg dac_enable = 'd0; + reg [15:0] dac_data_i0_0 = 'd0; + reg [15:0] dac_data_i0_1 = 'd0; + reg [15:0] dac_data_i0_2 = 'd0; + reg [15:0] dac_data_i0_3 = 'd0; + reg [15:0] dac_data_q0_0 = 'd0; + reg [15:0] dac_data_q0_1 = 'd0; + reg [15:0] dac_data_q0_2 = 'd0; + reg [15:0] dac_data_q0_3 = 'd0; + reg [15:0] dac_data_i1_0 = 'd0; + reg [15:0] dac_data_i1_1 = 'd0; + reg [15:0] dac_data_i1_2 = 'd0; + reg [15:0] dac_data_i1_3 = 'd0; + reg [15:0] dac_data_q1_0 = 'd0; + reg [15:0] dac_data_q1_1 = 'd0; + reg [15:0] dac_data_q1_2 = 'd0; + reg [15:0] dac_data_q1_3 = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal signals + + wire dac_enable_s; + wire dac_datafmt_s; + wire [ 3:0] dac_datasel_s; + wire [15:0] dac_dds_data_0_0_s; + wire [15:0] dac_dds_data_0_1_s; + wire [15:0] dac_dds_data_0_2_s; + wire [15:0] dac_dds_data_0_3_s; + wire [15:0] dac_dds_data_1_0_s; + wire [15:0] dac_dds_data_1_1_s; + wire [15:0] dac_dds_data_1_2_s; + wire [15:0] dac_dds_data_1_3_s; + wire [15:0] dac_dds_data_2_0_s; + wire [15:0] dac_dds_data_2_1_s; + wire [15:0] dac_dds_data_2_2_s; + wire [15:0] dac_dds_data_2_3_s; + wire [15:0] dac_dds_data_3_0_s; + wire [15:0] dac_dds_data_3_1_s; + wire [15:0] dac_dds_data_3_2_s; + wire [15:0] dac_dds_data_3_3_s; + wire [31:0] up_rdata_0_s; + wire up_ack_0_s; + wire [31:0] up_rdata_1_s; + wire up_ack_1_s; + wire [31:0] up_rdata_2_s; + wire up_ack_2_s; + wire [31:0] up_rdata_3_s; + wire up_ack_3_s; + wire [31:0] up_rdata_s; + wire up_ack_s; + + // dac dma read + + assign dac_drd = dac_enable; + + always @(posedge dac_clk) begin + dac_enable <= dac_enable_s; + end + + // dac outputs + + always @(posedge dac_clk) begin + if (dac_datasel_s[3:1] == 3'd1) begin + dac_data_i0_0 <= dac_ddata[ 15: 0]; + dac_data_i0_1 <= dac_ddata[ 79: 64]; + dac_data_i0_2 <= dac_ddata[143:128]; + dac_data_i0_3 <= dac_ddata[207:192]; + dac_data_q0_0 <= dac_ddata[ 31: 16]; + dac_data_q0_1 <= dac_ddata[ 95: 80]; + dac_data_q0_2 <= dac_ddata[159:144]; + dac_data_q0_3 <= dac_ddata[223:208]; + dac_data_i1_0 <= dac_ddata[ 47: 32]; + dac_data_i1_1 <= dac_ddata[111: 96]; + dac_data_i1_2 <= dac_ddata[175:160]; + dac_data_i1_3 <= dac_ddata[239:224]; + dac_data_q1_0 <= dac_ddata[ 63: 48]; + dac_data_q1_1 <= dac_ddata[127:112]; + dac_data_q1_2 <= dac_ddata[191:176]; + dac_data_q1_3 <= dac_ddata[255:240]; + end else begin + dac_data_i0_0 <= dac_dds_data_0_0_s; + dac_data_i0_1 <= dac_dds_data_0_1_s; + dac_data_i0_2 <= dac_dds_data_0_2_s; + dac_data_i0_3 <= dac_dds_data_0_3_s; + dac_data_q0_0 <= dac_dds_data_1_0_s; + dac_data_q0_1 <= dac_dds_data_1_1_s; + dac_data_q0_2 <= dac_dds_data_1_2_s; + dac_data_q0_3 <= dac_dds_data_1_3_s; + dac_data_i1_0 <= dac_dds_data_2_0_s; + dac_data_i1_1 <= dac_dds_data_2_1_s; + dac_data_i1_2 <= dac_dds_data_2_2_s; + dac_data_i1_3 <= dac_dds_data_2_3_s; + dac_data_q1_0 <= dac_dds_data_3_0_s; + dac_data_q1_1 <= dac_dds_data_3_1_s; + dac_data_q1_2 <= dac_dds_data_3_2_s; + dac_data_q1_3 <= dac_dds_data_3_3_s; + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s; + up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s | up_ack_2_s | up_ack_3_s; + end + end + + // dac channel + + axi_ad9144_channel #( + .CHID(0), + .DP_DISABLE(DP_DISABLE)) + i_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_data_0 (dac_dds_data_0_0_s), + .dac_dds_data_1 (dac_dds_data_0_1_s), + .dac_dds_data_2 (dac_dds_data_0_2_s), + .dac_dds_data_3 (dac_dds_data_0_3_s), + .dac_dds_enable (dac_enable), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata_0_s), + .up_ack (up_ack_0_s)); + + // dac channel + + axi_ad9144_channel #( + .CHID(1), + .DP_DISABLE(DP_DISABLE)) + i_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_data_0 (dac_dds_data_1_0_s), + .dac_dds_data_1 (dac_dds_data_1_1_s), + .dac_dds_data_2 (dac_dds_data_1_2_s), + .dac_dds_data_3 (dac_dds_data_1_3_s), + .dac_dds_enable (dac_enable), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata_1_s), + .up_ack (up_ack_1_s)); + + // dac channel + + axi_ad9144_channel #( + .CHID(2), + .DP_DISABLE(DP_DISABLE)) + i_channel_2 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_data_0 (dac_dds_data_2_0_s), + .dac_dds_data_1 (dac_dds_data_2_1_s), + .dac_dds_data_2 (dac_dds_data_2_2_s), + .dac_dds_data_3 (dac_dds_data_2_3_s), + .dac_dds_enable (dac_enable), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata_2_s), + .up_ack (up_ack_2_s)); + + // dac channel + + axi_ad9144_channel #( + .CHID(3), + .DP_DISABLE(DP_DISABLE)) + i_channel_3 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_data_0 (dac_dds_data_3_0_s), + .dac_dds_data_1 (dac_dds_data_3_1_s), + .dac_dds_data_2 (dac_dds_data_3_2_s), + .dac_dds_data_3 (dac_dds_data_3_3_s), + .dac_dds_enable (dac_enable), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata_3_s), + .up_ack (up_ack_3_s)); + + // dac common processor interface + + up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_s), + .dac_frame (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datasel (dac_datasel_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd40), + .drp_clk (up_clk), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata_s), + .up_ack (up_ack_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9144/axi_ad9144_dds.v b/library/axi_ad9144/axi_ad9144_dds.v new file mode 100644 index 000000000..b42238060 --- /dev/null +++ b/library/axi_ad9144/axi_ad9144_dds.v @@ -0,0 +1,597 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9144_dds ( + + // dac interface + + dac_clk, + dac_rst, + dac_dds_data_0, + dac_dds_data_1, + dac_dds_data_2, + dac_dds_data_3, + + // processor interface + + dac_dds_enable, + dac_dds_format, + dac_dds_sel, + dac_dds_patt_1, + dac_dds_init_1, + dac_dds_incr_1, + dac_dds_scale_1, + dac_dds_patt_2, + dac_dds_init_2, + dac_dds_incr_2, + dac_dds_scale_2); + + // parameters + + parameter DP_DISABLE = 0; + + // dac interface + + input dac_clk; + input dac_rst; + output [15:0] dac_dds_data_0; + output [15:0] dac_dds_data_1; + output [15:0] dac_dds_data_2; + output [15:0] dac_dds_data_3; + + // processor interface + + input dac_dds_enable; + input dac_dds_format; + input [ 3:0] dac_dds_sel; + input [15:0] dac_dds_patt_1; + input [15:0] dac_dds_init_1; + input [15:0] dac_dds_incr_1; + input [15:0] dac_dds_scale_1; + input [15:0] dac_dds_patt_2; + input [15:0] dac_dds_init_2; + input [15:0] dac_dds_incr_2; + input [15:0] dac_dds_scale_2; + + // internal registers + + reg [63:0] dac_pn7 = 'd0; + reg [63:0] dac_pn15 = 'd0; + reg [63:0] dac_pn23 = 'd0; + reg [63:0] dac_pn31 = 'd0; + reg [15:0] dac_dds_phase_0_0 = 'd0; + reg [15:0] dac_dds_phase_0_1 = 'd0; + reg [15:0] dac_dds_phase_1_0 = 'd0; + reg [15:0] dac_dds_phase_1_1 = 'd0; + reg [15:0] dac_dds_phase_2_0 = 'd0; + reg [15:0] dac_dds_phase_2_1 = 'd0; + reg [15:0] dac_dds_phase_3_0 = 'd0; + reg [15:0] dac_dds_phase_3_1 = 'd0; + reg [15:0] dac_dds_data_0 = 'd0; + reg [15:0] dac_dds_data_1 = 'd0; + reg [15:0] dac_dds_data_2 = 'd0; + reg [15:0] dac_dds_data_3 = 'd0; + + // internal signals + + wire [15:0] dac_dds_data_0_s; + wire [15:0] dac_dds_data_1_s; + wire [15:0] dac_dds_data_2_s; + wire [15:0] dac_dds_data_3_s; + + // pn7 function + + function [63:0] pn7; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[ 7] ^ din[ 6]; + dout[62] = din[ 6] ^ din[ 5]; + dout[61] = din[ 5] ^ din[ 4]; + dout[60] = din[ 4] ^ din[ 3]; + dout[59] = din[ 3] ^ din[ 2]; + dout[58] = din[ 2] ^ din[ 1]; + dout[57] = din[ 1] ^ din[ 0]; + dout[56] = din[ 0] ^ din[ 7] ^ din[ 6]; + dout[55] = din[ 7] ^ din[ 5]; + dout[54] = din[ 6] ^ din[ 4]; + dout[53] = din[ 5] ^ din[ 3]; + dout[52] = din[ 4] ^ din[ 2]; + dout[51] = din[ 3] ^ din[ 1]; + dout[50] = din[ 2] ^ din[ 0]; + dout[49] = din[ 1] ^ din[ 7] ^ din[ 6]; + dout[48] = din[ 0] ^ din[ 6] ^ din[ 5]; + dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6]; + dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5]; + dout[40] = din[ 0] ^ din[ 7] ^ din[ 4]; + dout[39] = din[ 7] ^ din[ 3]; + dout[38] = din[ 6] ^ din[ 2]; + dout[37] = din[ 5] ^ din[ 1]; + dout[36] = din[ 4] ^ din[ 0]; + dout[35] = din[ 3] ^ din[ 7] ^ din[ 6]; + dout[34] = din[ 2] ^ din[ 6] ^ din[ 5]; + dout[33] = din[ 1] ^ din[ 5] ^ din[ 4]; + dout[32] = din[ 0] ^ din[ 4] ^ din[ 3]; + dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; + dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6]; + dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5]; + dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4]; + dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3]; + dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6]; + dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; + dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4]; + dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3]; + dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; + dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; + dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7]; + dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2]; + dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1]; + dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[10] = din[ 0] ^ din[ 1] ^ din[ 7]; + dout[ 9] = din[ 7] ^ din[ 0]; + dout[ 8] = din[ 7]; + dout[ 7] = din[ 6]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 4]; + dout[ 4] = din[ 3]; + dout[ 3] = din[ 2]; + dout[ 2] = din[ 1]; + dout[ 1] = din[ 0]; + dout[ 0] = din[ 7] ^ din[ 6]; + pn7 = dout; + end + endfunction + + // pn15 function + + function [63:0] pn15; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[15] ^ din[14]; + dout[62] = din[14] ^ din[13]; + dout[61] = din[13] ^ din[12]; + dout[60] = din[12] ^ din[11]; + dout[59] = din[11] ^ din[10]; + dout[58] = din[10] ^ din[ 9]; + dout[57] = din[ 9] ^ din[ 8]; + dout[56] = din[ 8] ^ din[ 7]; + dout[55] = din[ 7] ^ din[ 6]; + dout[54] = din[ 6] ^ din[ 5]; + dout[53] = din[ 5] ^ din[ 4]; + dout[52] = din[ 4] ^ din[ 3]; + dout[51] = din[ 3] ^ din[ 2]; + dout[50] = din[ 2] ^ din[ 1]; + dout[49] = din[ 1] ^ din[ 0]; + dout[48] = din[ 0] ^ din[15] ^ din[14]; + dout[47] = din[15] ^ din[13]; + dout[46] = din[14] ^ din[12]; + dout[45] = din[13] ^ din[11]; + dout[44] = din[12] ^ din[10]; + dout[43] = din[11] ^ din[ 9]; + dout[42] = din[10] ^ din[ 8]; + dout[41] = din[ 9] ^ din[ 7]; + dout[40] = din[ 8] ^ din[ 6]; + dout[39] = din[ 7] ^ din[ 5]; + dout[38] = din[ 6] ^ din[ 4]; + dout[37] = din[ 5] ^ din[ 3]; + dout[36] = din[ 4] ^ din[ 2]; + dout[35] = din[ 3] ^ din[ 1]; + dout[34] = din[ 2] ^ din[ 0]; + dout[33] = din[ 1] ^ din[15] ^ din[14]; + dout[32] = din[ 0] ^ din[14] ^ din[13]; + dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12]; + dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11]; + dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10]; + dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; + dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; + dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; + dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; + dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; + dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; + dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; + dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; + dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; + dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; + dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14]; + dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13]; + dout[16] = din[ 0] ^ din[15] ^ din[12]; + dout[15] = din[15] ^ din[11]; + dout[14] = din[14] ^ din[10]; + dout[13] = din[13] ^ din[ 9]; + dout[12] = din[12] ^ din[ 8]; + dout[11] = din[11] ^ din[ 7]; + dout[10] = din[10] ^ din[ 6]; + dout[ 9] = din[ 9] ^ din[ 5]; + dout[ 8] = din[ 8] ^ din[ 4]; + dout[ 7] = din[ 7] ^ din[ 3]; + dout[ 6] = din[ 6] ^ din[ 2]; + dout[ 5] = din[ 5] ^ din[ 1]; + dout[ 4] = din[ 4] ^ din[ 0]; + dout[ 3] = din[ 3] ^ din[15] ^ din[14]; + dout[ 2] = din[ 2] ^ din[14] ^ din[13]; + dout[ 1] = din[ 1] ^ din[13] ^ din[12]; + dout[ 0] = din[ 0] ^ din[12] ^ din[11]; + pn15 = dout; + end + endfunction + + // pn23 function + + function [63:0] pn23; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[23] ^ din[18]; + dout[62] = din[22] ^ din[17]; + dout[61] = din[21] ^ din[16]; + dout[60] = din[20] ^ din[15]; + dout[59] = din[19] ^ din[14]; + dout[58] = din[18] ^ din[13]; + dout[57] = din[17] ^ din[12]; + dout[56] = din[16] ^ din[11]; + dout[55] = din[15] ^ din[10]; + dout[54] = din[14] ^ din[ 9]; + dout[53] = din[13] ^ din[ 8]; + dout[52] = din[12] ^ din[ 7]; + dout[51] = din[11] ^ din[ 6]; + dout[50] = din[10] ^ din[ 5]; + dout[49] = din[ 9] ^ din[ 4]; + dout[48] = din[ 8] ^ din[ 3]; + dout[47] = din[ 7] ^ din[ 2]; + dout[46] = din[ 6] ^ din[ 1]; + dout[45] = din[ 5] ^ din[ 0]; + dout[44] = din[ 4] ^ din[23] ^ din[18]; + dout[43] = din[ 3] ^ din[22] ^ din[17]; + dout[42] = din[ 2] ^ din[21] ^ din[16]; + dout[41] = din[ 1] ^ din[20] ^ din[15]; + dout[40] = din[ 0] ^ din[19] ^ din[14]; + dout[39] = din[23] ^ din[13]; + dout[38] = din[22] ^ din[12]; + dout[37] = din[21] ^ din[11]; + dout[36] = din[20] ^ din[10]; + dout[35] = din[19] ^ din[ 9]; + dout[34] = din[18] ^ din[ 8]; + dout[33] = din[17] ^ din[ 7]; + dout[32] = din[16] ^ din[ 6]; + dout[31] = din[15] ^ din[ 5]; + dout[30] = din[14] ^ din[ 4]; + dout[29] = din[13] ^ din[ 3]; + dout[28] = din[12] ^ din[ 2]; + dout[27] = din[11] ^ din[ 1]; + dout[26] = din[10] ^ din[ 0]; + dout[25] = din[ 9] ^ din[23] ^ din[18]; + dout[24] = din[ 8] ^ din[22] ^ din[17]; + dout[23] = din[ 7] ^ din[21] ^ din[16]; + dout[22] = din[ 6] ^ din[20] ^ din[15]; + dout[21] = din[ 5] ^ din[19] ^ din[14]; + dout[20] = din[ 4] ^ din[18] ^ din[13]; + dout[19] = din[ 3] ^ din[17] ^ din[12]; + dout[18] = din[ 2] ^ din[16] ^ din[11]; + dout[17] = din[ 1] ^ din[15] ^ din[10]; + dout[16] = din[ 0] ^ din[14] ^ din[ 9]; + dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8]; + dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18]; + dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17]; + dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16]; + dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15]; + dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14]; + dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13]; + dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12]; + pn23 = dout; + end + endfunction + + // pn31 function + + function [63:0] pn31; + input [63:0] din; + reg [63:0] dout; + begin + dout[63] = din[31] ^ din[28]; + dout[62] = din[30] ^ din[27]; + dout[61] = din[29] ^ din[26]; + dout[60] = din[28] ^ din[25]; + dout[59] = din[27] ^ din[24]; + dout[58] = din[26] ^ din[23]; + dout[57] = din[25] ^ din[22]; + dout[56] = din[24] ^ din[21]; + dout[55] = din[23] ^ din[20]; + dout[54] = din[22] ^ din[19]; + dout[53] = din[21] ^ din[18]; + dout[52] = din[20] ^ din[17]; + dout[51] = din[19] ^ din[16]; + dout[50] = din[18] ^ din[15]; + dout[49] = din[17] ^ din[14]; + dout[48] = din[16] ^ din[13]; + dout[47] = din[15] ^ din[12]; + dout[46] = din[14] ^ din[11]; + dout[45] = din[13] ^ din[10]; + dout[44] = din[12] ^ din[ 9]; + dout[43] = din[11] ^ din[ 8]; + dout[42] = din[10] ^ din[ 7]; + dout[41] = din[ 9] ^ din[ 6]; + dout[40] = din[ 8] ^ din[ 5]; + dout[39] = din[ 7] ^ din[ 4]; + dout[38] = din[ 6] ^ din[ 3]; + dout[37] = din[ 5] ^ din[ 2]; + dout[36] = din[ 4] ^ din[ 1]; + dout[35] = din[ 3] ^ din[ 0]; + dout[34] = din[ 2] ^ din[31] ^ din[28]; + dout[33] = din[ 1] ^ din[30] ^ din[27]; + dout[32] = din[ 0] ^ din[29] ^ din[26]; + dout[31] = din[31] ^ din[25]; + dout[30] = din[30] ^ din[24]; + dout[29] = din[29] ^ din[23]; + dout[28] = din[28] ^ din[22]; + dout[27] = din[27] ^ din[21]; + dout[26] = din[26] ^ din[20]; + dout[25] = din[25] ^ din[19]; + dout[24] = din[24] ^ din[18]; + dout[23] = din[23] ^ din[17]; + dout[22] = din[22] ^ din[16]; + dout[21] = din[21] ^ din[15]; + dout[20] = din[20] ^ din[14]; + dout[19] = din[19] ^ din[13]; + dout[18] = din[18] ^ din[12]; + dout[17] = din[17] ^ din[11]; + dout[16] = din[16] ^ din[10]; + dout[15] = din[15] ^ din[ 9]; + dout[14] = din[14] ^ din[ 8]; + dout[13] = din[13] ^ din[ 7]; + dout[12] = din[12] ^ din[ 6]; + dout[11] = din[11] ^ din[ 5]; + dout[10] = din[10] ^ din[ 4]; + dout[ 9] = din[ 9] ^ din[ 3]; + dout[ 8] = din[ 8] ^ din[ 2]; + dout[ 7] = din[ 7] ^ din[ 1]; + dout[ 6] = din[ 6] ^ din[ 0]; + dout[ 5] = din[ 5] ^ din[31] ^ din[28]; + dout[ 4] = din[ 4] ^ din[30] ^ din[27]; + dout[ 3] = din[ 3] ^ din[29] ^ din[26]; + dout[ 2] = din[ 2] ^ din[28] ^ din[25]; + dout[ 1] = din[ 1] ^ din[27] ^ din[24]; + dout[ 0] = din[ 0] ^ din[26] ^ din[23]; + pn31 = dout; + end + endfunction + + // dds output scaling (shift only) + + function [15:0] dac_datascale; + input [15:0] data; + input [ 3:0] scale; + reg [15:0] data_out; + begin + case (scale) + 4'b1111: data_out = {{15{data[15]}}, data[15:15]}; + 4'b1110: data_out = {{14{data[15]}}, data[15:14]}; + 4'b1101: data_out = {{13{data[15]}}, data[15:13]}; + 4'b1100: data_out = {{12{data[15]}}, data[15:12]}; + 4'b1011: data_out = {{11{data[15]}}, data[15:11]}; + 4'b1010: data_out = {{10{data[15]}}, data[15:10]}; + 4'b1001: data_out = {{ 9{data[15]}}, data[15: 9]}; + 4'b1000: data_out = {{ 8{data[15]}}, data[15: 8]}; + 4'b0111: data_out = {{ 7{data[15]}}, data[15: 7]}; + 4'b0110: data_out = {{ 6{data[15]}}, data[15: 6]}; + 4'b0101: data_out = {{ 5{data[15]}}, data[15: 5]}; + 4'b0100: data_out = {{ 4{data[15]}}, data[15: 4]}; + 4'b0011: data_out = {{ 3{data[15]}}, data[15: 3]}; + 4'b0010: data_out = {{ 2{data[15]}}, data[15: 2]}; + 4'b0001: data_out = {{ 1{data[15]}}, data[15: 1]}; + default: data_out = data; + endcase + dac_datascale = data_out; + end + endfunction + + // pn registers + + always @(posedge dac_clk) begin + if (dac_dds_enable == 1'b0) begin + dac_pn7 <= {64{1'd1}}; + dac_pn15 <= {64{1'd1}}; + dac_pn23 <= {64{1'd1}}; + dac_pn31 <= {64{1'd1}}; + end else begin + dac_pn7 <= pn7(dac_pn7); + dac_pn15 <= pn15(dac_pn15); + dac_pn23 <= pn23(dac_pn23); + dac_pn31 <= pn31(dac_pn31); + end + end + + // dds phase counters + + always @(posedge dac_clk) begin + if (dac_dds_enable == 1'b0) begin + dac_dds_phase_0_0 <= dac_dds_init_1; + dac_dds_phase_0_1 <= dac_dds_init_2; + dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1; + dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2; + dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1; + dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2; + dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1; + dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2; + end else begin + dac_dds_phase_0_0 <= dac_dds_phase_0_0 + {dac_dds_incr_1[13:0], 2'd0}; + dac_dds_phase_0_1 <= dac_dds_phase_0_1 + {dac_dds_incr_2[13:0], 2'd0}; + dac_dds_phase_1_0 <= dac_dds_phase_1_0 + {dac_dds_incr_1[13:0], 2'd0}; + dac_dds_phase_1_1 <= dac_dds_phase_1_1 + {dac_dds_incr_2[13:0], 2'd0}; + dac_dds_phase_2_0 <= dac_dds_phase_2_0 + {dac_dds_incr_1[13:0], 2'd0}; + dac_dds_phase_2_1 <= dac_dds_phase_2_1 + {dac_dds_incr_2[13:0], 2'd0}; + dac_dds_phase_3_0 <= dac_dds_phase_3_0 + {dac_dds_incr_1[13:0], 2'd0}; + dac_dds_phase_3_1 <= dac_dds_phase_3_1 + {dac_dds_incr_2[13:0], 2'd0}; + end + end + + // output is either 2's complement or offset binary. + + always @(posedge dac_clk) begin + case (dac_dds_sel) + 4'b0111: begin + dac_dds_data_0 <= dac_pn31[15: 0]; + dac_dds_data_1 <= dac_pn31[31:16]; + dac_dds_data_2 <= dac_pn31[47:32]; + dac_dds_data_3 <= dac_pn31[63:48]; + end + 4'b0110: begin + dac_dds_data_0 <= dac_pn23[15: 0]; + dac_dds_data_1 <= dac_pn23[31:16]; + dac_dds_data_2 <= dac_pn23[47:32]; + dac_dds_data_3 <= dac_pn23[63:48]; + end + 4'b0101: begin + dac_dds_data_0 <= dac_pn15[15: 0]; + dac_dds_data_1 <= dac_pn15[31:16]; + dac_dds_data_2 <= dac_pn15[47:32]; + dac_dds_data_3 <= dac_pn15[63:48]; + end + 4'b0100: begin + dac_dds_data_0 <= dac_pn7[15: 0]; + dac_dds_data_1 <= dac_pn7[31:16]; + dac_dds_data_2 <= dac_pn7[47:32]; + dac_dds_data_3 <= dac_pn7[63:48]; + end + 4'b0001: begin + dac_dds_data_0 <= dac_dds_patt_1; + dac_dds_data_1 <= dac_dds_patt_2; + dac_dds_data_2 <= dac_dds_patt_1; + dac_dds_data_3 <= dac_dds_patt_2; + end + default: begin + dac_dds_data_0 <= dac_dds_data_0_s; + dac_dds_data_1 <= dac_dds_data_1_s; + dac_dds_data_2 <= dac_dds_data_2_s; + dac_dds_data_3 <= dac_dds_data_3_s; + end + endcase + end + + // dds + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_0_s = 16'd0; + end else begin + ad_dds i_dds_0 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_enable (dac_dds_enable), + .dds_phase_0 (dac_dds_phase_0_0), + .dds_scale_0 (dac_dds_scale_1), + .dds_phase_1 (dac_dds_phase_0_1), + .dds_scale_1 (dac_dds_scale_2), + .dds_data (dac_dds_data_0_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_1_s = 16'd0; + end else begin + ad_dds i_dds_1 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_enable (dac_dds_enable), + .dds_phase_0 (dac_dds_phase_1_0), + .dds_scale_0 (dac_dds_scale_1), + .dds_phase_1 (dac_dds_phase_1_1), + .dds_scale_1 (dac_dds_scale_2), + .dds_data (dac_dds_data_1_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_2_s = 16'd0; + end else begin + ad_dds i_dds_2 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_enable (dac_dds_enable), + .dds_phase_0 (dac_dds_phase_2_0), + .dds_scale_0 (dac_dds_scale_1), + .dds_phase_1 (dac_dds_phase_2_1), + .dds_scale_1 (dac_dds_scale_2), + .dds_data (dac_dds_data_2_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign dac_dds_data_3_s = 16'd0; + end else begin + ad_dds i_dds_3 ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_enable (dac_dds_enable), + .dds_phase_0 (dac_dds_phase_3_0), + .dds_scale_0 (dac_dds_scale_1), + .dds_phase_1 (dac_dds_phase_3_1), + .dds_scale_1 (dac_dds_scale_2), + .dds_data (dac_dds_data_3_s)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9144/axi_ad9144_if.v b/library/axi_ad9144/axi_ad9144_if.v new file mode 100644 index 000000000..2d9c5f4f4 --- /dev/null +++ b/library/axi_ad9144/axi_ad9144_if.v @@ -0,0 +1,150 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the dac physical interface (drives samples from the low speed clock to the +// dac clock domain. + +`timescale 1ns/100ps + +module axi_ad9144_if ( + + // jesd interface + // tx_clk is (line-rate/40) + + tx_clk, + tx_data, + + // dac interface + + dac_clk, + dac_rst, + dac_data_i0_0, + dac_data_i0_1, + dac_data_i0_2, + dac_data_i0_3, + dac_data_q0_0, + dac_data_q0_1, + dac_data_q0_2, + dac_data_q0_3, + dac_data_i1_0, + dac_data_i1_1, + dac_data_i1_2, + dac_data_i1_3, + dac_data_q1_0, + dac_data_q1_1, + dac_data_q1_2, + dac_data_q1_3); + + // jesd interface + // tx_clk is (line-rate/40) + + input tx_clk; + output [255:0] tx_data; + + // dac interface + + output dac_clk; + input dac_rst; + input [15:0] dac_data_i0_0; + input [15:0] dac_data_i0_1; + input [15:0] dac_data_i0_2; + input [15:0] dac_data_i0_3; + input [15:0] dac_data_q0_0; + input [15:0] dac_data_q0_1; + input [15:0] dac_data_q0_2; + input [15:0] dac_data_q0_3; + input [15:0] dac_data_i1_0; + input [15:0] dac_data_i1_1; + input [15:0] dac_data_i1_2; + input [15:0] dac_data_i1_3; + input [15:0] dac_data_q1_0; + input [15:0] dac_data_q1_1; + input [15:0] dac_data_q1_2; + input [15:0] dac_data_q1_3; + + // internal registers + + reg [255:0] tx_data = 'd0; + + // reorder data for the jesd links + + assign dac_clk = tx_clk; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + tx_data <= 256'd0; + end else begin + tx_data[255:248] <= dac_data_q1_3[ 7: 0]; + tx_data[247:240] <= dac_data_q1_2[ 7: 0]; + tx_data[239:232] <= dac_data_q1_1[ 7: 0]; + tx_data[231:224] <= dac_data_q1_0[ 7: 0]; + tx_data[223:216] <= dac_data_q1_3[15: 8]; + tx_data[215:208] <= dac_data_q1_2[15: 8]; + tx_data[207:200] <= dac_data_q1_1[15: 8]; + tx_data[199:192] <= dac_data_q1_0[15: 8]; + tx_data[191:184] <= dac_data_i1_3[ 7: 0]; + tx_data[183:176] <= dac_data_i1_2[ 7: 0]; + tx_data[175:168] <= dac_data_i1_1[ 7: 0]; + tx_data[167:160] <= dac_data_i1_0[ 7: 0]; + tx_data[159:152] <= dac_data_i1_3[15: 8]; + tx_data[151:144] <= dac_data_i1_2[15: 8]; + tx_data[143:136] <= dac_data_i1_1[15: 8]; + tx_data[135:128] <= dac_data_i1_0[15: 8]; + tx_data[127:120] <= dac_data_q0_3[ 7: 0]; + tx_data[119:112] <= dac_data_q0_2[ 7: 0]; + tx_data[111:104] <= dac_data_q0_1[ 7: 0]; + tx_data[103: 96] <= dac_data_q0_0[ 7: 0]; + tx_data[ 95: 88] <= dac_data_q0_3[15: 8]; + tx_data[ 87: 80] <= dac_data_q0_2[15: 8]; + tx_data[ 79: 72] <= dac_data_q0_1[15: 8]; + tx_data[ 71: 64] <= dac_data_q0_0[15: 8]; + tx_data[ 63: 56] <= dac_data_i0_3[ 7: 0]; + tx_data[ 55: 48] <= dac_data_i0_2[ 7: 0]; + tx_data[ 47: 40] <= dac_data_i0_1[ 7: 0]; + tx_data[ 39: 32] <= dac_data_i0_0[ 7: 0]; + tx_data[ 31: 24] <= dac_data_i0_3[15: 8]; + tx_data[ 23: 16] <= dac_data_i0_2[15: 8]; + tx_data[ 15: 8] <= dac_data_i0_1[15: 8]; + tx_data[ 7: 0] <= dac_data_i0_0[15: 8]; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl new file mode 100644 index 000000000..2f8162f98 --- /dev/null +++ b/library/axi_ad9144/axi_ad9144_ip.tcl @@ -0,0 +1,29 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9144 +adi_ip_files axi_ad9144 [list \ + "$ad_hdl_dir/library/common/ad_mul_u16.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9144_dds.v" \ + "axi_ad9144_channel.v" \ + "axi_ad9144_core.v" \ + "axi_ad9144_if.v" \ + "axi_ad9144.v" ] + +adi_ip_properties axi_ad9144 + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v new file mode 100644 index 000000000..681986b93 --- /dev/null +++ b/library/axi_ad9680/axi_ad9680.v @@ -0,0 +1,379 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9680 ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_dwr, + adc_ddata, + adc_dsync, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready, + + // debug signals + + adc_mon_valid, + adc_mon_data); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_BASEADDR = 32'hffffffff; + parameter C_HIGHADDR = 32'h00000000; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // dma interface + + output adc_clk; + output adc_dwr; + output [127:0] adc_ddata; + output adc_dsync; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // debug signals + + output adc_mon_valid; + output [239:0] adc_mon_data; + + // internal registers + + reg adc_data_cnt = 'd0; + reg adc_dsync = 'd0; + reg adc_dwr = 'd0; + reg [127:0] adc_ddata = 'd0; + reg up_adc_status_pn_err = 'd0; + reg up_adc_status_pn_oos = 'd0; + reg up_adc_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [55:0] adc_data_a_s; + wire [55:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire adc_status_s; + wire adc_enable_a_s; + wire [63:0] adc_channel_data_a_s; + wire adc_enable_b_s; + wire [63:0] adc_channel_data_b_s; + wire up_adc_pn_err_a_s; + wire up_adc_pn_oos_a_s; + wire up_adc_or_a_s; + wire [31:0] up_adc_channel_rdata_a_s; + wire up_adc_channel_ack_a_s; + wire up_adc_pn_err_b_s; + wire up_adc_pn_oos_b_s; + wire up_adc_or_b_s; + wire [31:0] up_adc_channel_rdata_b_s; + wire up_adc_channel_ack_b_s; + wire [31:0] up_adc_common_rdata_s; + wire up_adc_common_ack_s; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // monitor signals + + assign adc_mon_valid = 1'b1; + assign adc_mon_data[ 63: 0] = adc_channel_data_a_s; + assign adc_mon_data[127: 64] = adc_channel_data_b_s; + assign adc_mon_data[183:128] = adc_data_a_s; + assign adc_mon_data[239:184] = adc_data_b_s; + + // adc channels - dma interface + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt; + case ({adc_enable_b_s, adc_enable_a_s}) + 2'b11: begin // both I and Q + adc_dsync <= 1'b1; + adc_dwr <= 1'b1; + adc_ddata <= {adc_channel_data_b_s[63:48], adc_channel_data_a_s[63:48], + adc_channel_data_b_s[47:32], adc_channel_data_a_s[47:32], + adc_channel_data_b_s[31:16], adc_channel_data_a_s[31:16], + adc_channel_data_b_s[15: 0], adc_channel_data_a_s[15: 0]}; + end + 2'b10: begin // Q only + adc_dsync <= 1'b1; + adc_dwr <= adc_data_cnt; + adc_ddata <= {adc_channel_data_b_s, adc_ddata[127:64]}; + end + 2'b01: begin // I only + adc_dsync <= 1'b1; + adc_dwr <= adc_data_cnt; + adc_ddata <= {adc_channel_data_a_s, adc_ddata[127:64]}; + end + default: begin // no channels + adc_dsync <= 1'b1; + adc_dwr <= 1'b1; + adc_ddata <= {8{16'hdead}}; + end + endcase + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_status_pn_err <= 'd0; + up_adc_status_pn_oos <= 'd0; + up_adc_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s; + up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s; + up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s; + up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s; + up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s; + end + end + + // main (device interface) + + axi_ad9680_if i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s)); + + // channel + + axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dfmt_data (adc_channel_data_a_s), + .adc_enable (adc_enable_a_s), + .up_adc_pn_err (up_adc_pn_err_a_s), + .up_adc_pn_oos (up_adc_pn_oos_a_s), + .up_adc_or (up_adc_or_a_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_channel_rdata_a_s), + .up_ack (up_adc_channel_ack_a_s)); + + // channel + + axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dfmt_data (adc_channel_data_b_s), + .adc_enable (adc_enable_b_s), + .up_adc_pn_err (up_adc_pn_err_b_s), + .up_adc_pn_oos (up_adc_pn_oos_b_s), + .up_adc_or (up_adc_or_b_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_channel_rdata_b_s), + .up_ack (up_adc_channel_ack_b_s)); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_pn_err (up_adc_status_pn_err), + .adc_status_pn_oos (up_adc_status_pn_oos), + .adc_status_or (up_adc_status_or), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd40), + .delay_clk (1'b0), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (5'd0), + .delay_ack_t (1'b0), + .delay_locked (1'b1), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_adc_common_rdata_s), + .up_ack (up_adc_common_ack_s)); + + // up bus interface + + up_axi #( + .PCORE_BASEADDR (C_BASEADDR), + .PCORE_HIGHADDR (C_HIGHADDR)) + i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9680/axi_ad9680_channel.v b/library/axi_ad9680/axi_ad9680_channel.v new file mode 100644 index 000000000..1b4249790 --- /dev/null +++ b/library/axi_ad9680/axi_ad9680_channel.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9680_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [55:0] adc_data; + input adc_or; + + // channel interface + + output [63:0] adc_dfmt_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_pn_type_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + + // instantiations + + axi_ad9680_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_type (adc_pn_type_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_pn_sel (), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_pn_type (adc_pn_type_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9680/axi_ad9680_if.v b/library/axi_ad9680/axi_ad9680_if.v new file mode 100644 index 000000000..c658b6b84 --- /dev/null +++ b/library/axi_ad9680/axi_ad9680_if.v @@ -0,0 +1,132 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9680_if ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // adc data output + + adc_clk, + adc_rst, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status); + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // adc data output + + output adc_clk; + input adc_rst; + output [55:0] adc_data_a; + output [55:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // internal registers + + reg adc_status = 'd0; + + // internal signals + + wire [15:0] adc_data_a_s3_s; + wire [15:0] adc_data_a_s2_s; + wire [15:0] adc_data_a_s1_s; + wire [15:0] adc_data_a_s0_s; + wire [15:0] adc_data_b_s3_s; + wire [15:0] adc_data_b_s2_s; + wire [15:0] adc_data_b_s1_s; + wire [15:0] adc_data_b_s0_s; + + // adc clock is the reference clock + + assign adc_clk = rx_clk; + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + // adc channels + + assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0], + adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; + + assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0], + adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; + + // data multiplex + + assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]}; + assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]}; + assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]}; + assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]}; + + assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]}; + assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]}; + assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]}; + assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]}; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl new file mode 100644 index 000000000..8cde42fc0 --- /dev/null +++ b/library/axi_ad9680/axi_ad9680_ip.tcl @@ -0,0 +1,26 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9680 +adi_ip_files axi_ad9680 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9680_pnmon.v" \ + "axi_ad9680_channel.v" \ + "axi_ad9680_if.v" \ + "axi_ad9680.v" ] + +adi_ip_properties axi_ad9680 + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9680/axi_ad9680_pnmon.v b/library/axi_ad9680/axi_ad9680_pnmon.v new file mode 100644 index 000000000..c7f98c5ba --- /dev/null +++ b/library/axi_ad9680/axi_ad9680_pnmon.v @@ -0,0 +1,283 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9680_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pn_type); + + // adc interface + + input adc_clk; + input [55:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input adc_pn_type; + + // internal registers + + reg [55:0] adc_pn_data = 'd0; + reg adc_pn_match_d_1 = 'd0; + reg adc_pn_match_d_0 = 'd0; + reg adc_pn_match_z = 'd0; + reg adc_pn_err = 'd0; + reg [ 6:0] adc_pn_oos_count = 'd0; + reg adc_pn_oos = 'd0; + + // internal signals + + wire [55:0] adc_pn_data_in_s; + wire adc_pn_match_d_1_s; + wire adc_pn_match_d_0_s; + wire adc_pn_match_z_s; + wire adc_pn_match_s; + wire [55:0] adc_pn_data_s; + wire adc_pn_update_s; + wire adc_pn_err_s; + + // PN23 function + + function [55:0] pn23; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[22] ^ din[17]; + dout[54] = din[21] ^ din[16]; + dout[53] = din[20] ^ din[15]; + dout[52] = din[19] ^ din[14]; + dout[51] = din[18] ^ din[13]; + dout[50] = din[17] ^ din[12]; + dout[49] = din[16] ^ din[11]; + dout[48] = din[15] ^ din[10]; + dout[47] = din[14] ^ din[ 9]; + dout[46] = din[13] ^ din[ 8]; + dout[45] = din[12] ^ din[ 7]; + dout[44] = din[11] ^ din[ 6]; + dout[43] = din[10] ^ din[ 5]; + dout[42] = din[ 9] ^ din[ 4]; + dout[41] = din[ 8] ^ din[ 3]; + dout[40] = din[ 7] ^ din[ 2]; + dout[39] = din[ 6] ^ din[ 1]; + dout[38] = din[ 5] ^ din[ 0]; + dout[37] = din[ 4] ^ din[22] ^ din[17]; + dout[36] = din[ 3] ^ din[21] ^ din[16]; + dout[35] = din[ 2] ^ din[20] ^ din[15]; + dout[34] = din[ 1] ^ din[19] ^ din[14]; + dout[33] = din[ 0] ^ din[18] ^ din[13]; + dout[32] = din[22] ^ din[12]; + dout[31] = din[21] ^ din[11]; + dout[30] = din[20] ^ din[10]; + dout[29] = din[19] ^ din[ 9]; + dout[28] = din[18] ^ din[ 8]; + dout[27] = din[17] ^ din[ 7]; + dout[26] = din[16] ^ din[ 6]; + dout[25] = din[15] ^ din[ 5]; + dout[24] = din[14] ^ din[ 4]; + dout[23] = din[13] ^ din[ 3]; + dout[22] = din[12] ^ din[ 2]; + dout[21] = din[11] ^ din[ 1]; + dout[20] = din[10] ^ din[ 0]; + dout[19] = din[ 9] ^ din[22] ^ din[17]; + dout[18] = din[ 8] ^ din[21] ^ din[16]; + dout[17] = din[ 7] ^ din[20] ^ din[15]; + dout[16] = din[ 6] ^ din[19] ^ din[14]; + dout[15] = din[ 5] ^ din[18] ^ din[13]; + dout[14] = din[ 4] ^ din[17] ^ din[12]; + dout[13] = din[ 3] ^ din[16] ^ din[11]; + dout[12] = din[ 2] ^ din[15] ^ din[10]; + dout[11] = din[ 1] ^ din[14] ^ din[ 9]; + dout[10] = din[ 0] ^ din[13] ^ din[ 8]; + dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17]; + dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [55:0] pn9; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[ 8] ^ din[ 4]; + dout[54] = din[ 7] ^ din[ 3]; + dout[53] = din[ 6] ^ din[ 2]; + dout[52] = din[ 5] ^ din[ 1]; + dout[51] = din[ 4] ^ din[ 0]; + dout[50] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[49] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[48] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[47] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[46] = din[ 8] ^ din[ 0]; + dout[45] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[44] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[43] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[42] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[41] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[26] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8]; + dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7]; + dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6]; + dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5]; + dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6]; + dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5]; + dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7]; + pn9 = dout; + end + endfunction + + // pn sequence checking algorithm is commonly used in most applications. + // if oos is asserted (pn is out of sync): + // the next sequence is generated from the incoming data. + // if 16 sequences match consecutively, oos is cleared (de-asserted). + // if oos is de-asserted (pn is in sync) + // the next sequence is generated from the current sequence. + // if 64 sequences mismatch consecutively, oos is set (asserted). + // if oos is de-asserted, any spurious mismatches sets the error register. + // ideally, processor should make sure both oos == 0x0 and err == 0x0. + + assign adc_pn_data_in_s = { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14], + ~adc_data[41], adc_data[40:28], + ~adc_data[55], adc_data[54:42]}; + assign adc_pn_match_d_1_s = (adc_pn_data_in_s[55:28] == adc_pn_data[55:28]) ? 1'b1 : 1'b0; + assign adc_pn_match_d_0_s = (adc_pn_data_in_s[27: 0] == adc_pn_data[27: 0]) ? 1'b1 : 1'b0; + assign adc_pn_match_z_s = (adc_pn_data_in_s == 56'd0) ? 1'b0 : 1'b1; + assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z; + assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data; + assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s); + assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s); + + // pn running sequence + + always @(posedge adc_clk) begin + if (adc_pn_type == 1'b0) begin + adc_pn_data <= pn9(adc_pn_data_s); + end else begin + adc_pn_data <= pn23(adc_pn_data_s); + end + end + + // pn oos and counters (64 to clear and set). + + always @(posedge adc_clk) begin + adc_pn_match_d_1 <= adc_pn_match_d_1_s; + adc_pn_match_d_0 <= adc_pn_match_d_0_s; + adc_pn_match_z <= adc_pn_match_z_s; + adc_pn_err <= adc_pn_err_s; + if (adc_pn_update_s == 1'b1) begin + if (adc_pn_oos_count >= 16) begin + adc_pn_oos_count <= 'd0; + adc_pn_oos <= ~adc_pn_oos; + end else begin + adc_pn_oos_count <= adc_pn_oos_count + 1'b1; + adc_pn_oos <= adc_pn_oos; + end + end else begin + adc_pn_oos_count <= 'd0; + adc_pn_oos <= adc_pn_oos; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/projects/ad9680_eval/common/ad9680_eval_bd.tcl b/projects/ad9680_eval/common/ad9680_eval_bd.tcl new file mode 100644 index 000000000..eb8166e1d --- /dev/null +++ b/projects/ad9680_eval/common/ad9680_eval_bd.tcl @@ -0,0 +1,188 @@ + +# ad9680 + +set spi_csn_i [create_bd_port -dir I spi_csn_i] +set spi_csn_o [create_bd_port -dir O spi_csn_o] +set spi_clk_i [create_bd_port -dir I spi_clk_i] +set spi_clk_o [create_bd_port -dir O spi_clk_o] +set spi_sdo_i [create_bd_port -dir I spi_sdo_i] +set spi_sdo_o [create_bd_port -dir O spi_sdo_o] +set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + +set rx_ref_clk [create_bd_port -dir I rx_ref_clk] +set rx_sync [create_bd_port -dir O rx_sync] +set rx_sysref [create_bd_port -dir O rx_sysref] +set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] +set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + +# adc peripherals + +set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + +set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd +set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + +set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma + +set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect + +# dac/adc common gt/gpio + +set axi_ad9680_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9680_gt] +set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_ad9680_gt + +set axi_ad9680_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_gt_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_gt_interconnect + +set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + +# connections (spi and gpio) + +connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] +connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] +connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] +connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] +connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] +connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] +connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + +# connections (gt) + +connect_bd_net -net axi_ad9680_gt_ref_clk_q [get_bd_pins axi_ad9680_gt/ref_clk_q] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_ad9680_gt_rx_data_p [get_bd_pins axi_ad9680_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_ad9680_gt_rx_data_n [get_bd_pins axi_ad9680_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_ad9680_gt_rx_sync [get_bd_pins axi_ad9680_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_ad9680_gt_rx_sysref [get_bd_pins axi_ad9680_gt/rx_sysref] [get_bd_ports rx_sysref] + +# connections (adc) + +connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_gt/rx_clk] +connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] +connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + +connect_bd_net -net axi_ad9680_gt_rx_rst [get_bd_pins axi_ad9680_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] +connect_bd_net -net axi_ad9680_gt_rx_sysref [get_bd_pins axi_ad9680_jesd/rx_sysref] +connect_bd_net -net axi_ad9680_gt_rx_gt_charisk [get_bd_pins axi_ad9680_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] +connect_bd_net -net axi_ad9680_gt_rx_gt_disperr [get_bd_pins axi_ad9680_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] +connect_bd_net -net axi_ad9680_gt_rx_gt_notintable [get_bd_pins axi_ad9680_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] +connect_bd_net -net axi_ad9680_gt_rx_gt_data [get_bd_pins axi_ad9680_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] +connect_bd_net -net axi_ad9680_gt_rx_rst_done [get_bd_pins axi_ad9680_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] +connect_bd_net -net axi_ad9680_gt_rx_ip_comma_align [get_bd_pins axi_ad9680_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] +connect_bd_net -net axi_ad9680_gt_rx_ip_sync [get_bd_pins axi_ad9680_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] +connect_bd_net -net axi_ad9680_gt_rx_ip_sof [get_bd_pins axi_ad9680_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] +connect_bd_net -net axi_ad9680_gt_rx_ip_data [get_bd_pins axi_ad9680_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] +connect_bd_net -net axi_ad9680_gt_rx_data [get_bd_pins axi_ad9680_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] +connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core/adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] +connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] +connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + +# interconnect (cpu) + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_gt/s_axi] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +# gt uses hp3, and 100MHz clock for both DRP and AXI4 + +connect_bd_intf_net -intf_net axi_ad9680_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] +connect_bd_intf_net -intf_net axi_ad9680_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_gt/m_axi] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/M00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/m_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/drp_clk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt/m_axi_aresetn] + +# memory interconnects share the same clock (fclk2) + +set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] +set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] + +connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source + +# interconnect (mem/dac) + +connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] +connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +# ila + +set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + +connect_bd_net -net axi_ad9680_gt_rx_mon_data [get_bd_pins axi_ad9680_gt/rx_mon_data] +connect_bd_net -net axi_ad9680_gt_rx_mon_trigger [get_bd_pins axi_ad9680_gt/rx_mon_trigger] +connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] +connect_bd_net -net axi_ad9680_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] +connect_bd_net -net axi_ad9680_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] +connect_bd_net -net axi_ad9680_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + +# address map + +create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core +create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma +create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd +create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_gt/s_axi/axi_lite] SEG_data_ad9680_gt + +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm + diff --git a/projects/ad9680_eval/common/ad9680_eval_spi.v b/projects/ad9680_eval/common/ad9680_eval_spi.v new file mode 100644 index 000000000..76e976d2f --- /dev/null +++ b/projects/ad9680_eval/common/ad9680_eval_spi.v @@ -0,0 +1,109 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad9680_eval_spi ( + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_sdio); + + // 4 wire + + input spi_csn; + input spi_clk; + input spi_mosi; + output spi_miso; + + // 3 wire + + inout spi_sdio; + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + IOBUF i_iobuf_sdio ( + .T (spi_enable_s), + .I (spi_mosi), + .O (spi_miso), + .IO (spi_sdio)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad9680_eval/zc706/system_bd.tcl b/projects/ad9680_eval/zc706/system_bd.tcl new file mode 100644 index 000000000..567bc2dff --- /dev/null +++ b/projects/ad9680_eval/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/ad9680_eval_bd.tcl + diff --git a/projects/ad9680_eval/zc706/system_constr.xdc b/projects/ad9680_eval/zc706/system_constr.xdc new file mode 100644 index 000000000..370faf0f1 --- /dev/null +++ b/projects/ad9680_eval/zc706/system_constr.xdc @@ -0,0 +1,39 @@ + +# ad9680 + +set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A6 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A7 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C6 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C7 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A2 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A3 FMC_HPC_DP1_M2C_N + +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N + +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D8 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H7 FMC_HPC_LA02_P + +# clocks + +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_ad9680_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] + diff --git a/projects/ad9680_eval/zc706/system_project.tcl b/projects/ad9680_eval/zc706/system_project.tcl new file mode 100644 index 000000000..7487c6dd9 --- /dev/null +++ b/projects/ad9680_eval/zc706/system_project.tcl @@ -0,0 +1,16 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create ad9680_eval_zc706 +adi_project_files ad9680_eval_zc706 [list \ + "system_top.v" \ + "../common/ad9680_eval_spi.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run ad9680_eval_zc706 + + diff --git a/projects/ad9680_eval/zc706/system_top.v b/projects/ad9680_eval/zc706/system_top.v new file mode 100644 index 000000000..29bbdd205 --- /dev/null +++ b/projects/ad9680_eval/zc706/system_top.v @@ -0,0 +1,240 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + spi_csn, + spi_clk, + spi_sdio); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + output rx_sysref_p; + output rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + output spi_csn; + output spi_clk; + inout spi_sdio; + + // internal signals + + wire [14:0] gpio_i; + wire [14:0] gpio_o; + wire [14:0] gpio_t; + + wire spi_mosi; + wire spi_miso; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sysref ( + .I (1'b0), + .O (rx_sysref_p), + .OB (rx_sysref_n)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + genvar n; + generate + for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + ad9680_eval_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (1'b0), + .spi_clk_o (spi_clk), + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (1'b0), + .spi_sdo_o (spi_mosi)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl new file mode 100644 index 000000000..48fe2ed88 --- /dev/null +++ b/projects/daq2/common/daq2_bd.tcl @@ -0,0 +1,466 @@ + + # daq2 + + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_clk_i [create_bd_port -dir I spi_clk_i] + set spi_clk_o [create_bd_port -dir O spi_clk_o] + set spi_sdo_i [create_bd_port -dir I spi_sdo_i] + set spi_sdo_o [create_bd_port -dir O spi_sdo_o] + set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + + set rx_ref_clk [create_bd_port -dir I rx_ref_clk] + set rx_sync [create_bd_port -dir O rx_sync] + set rx_sysref [create_bd_port -dir I rx_sysref] + set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + + set tx_ref_clk [create_bd_port -dir I tx_ref_clk] + set tx_sync [create_bd_port -dir I tx_sync] + set tx_sysref [create_bd_port -dir I tx_sysref] + set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] + set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] + set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] + set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] +} + + # dac peripherals + + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] + set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core + + set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + + set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma + set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma +} else { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma +} + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +if {$sys_zynq == 1} { + + set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect +} + + # adc peripherals + + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +} else { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma +} + +if {$sys_zynq == 1} { + + set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect +} + + # dac/adc common gt/gpio + + set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + +if {$sys_zynq == 1} { + + set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect +} + + # gpio and spi + +if {$sys_zynq == 0} { + + set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + + set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio +} + + # additions to default configuration + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + +} else { + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +} + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect + set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc +} + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 42 [get_bd_ports GPIO_I] + set_property LEFT 42 [get_bd_ports GPIO_O] + set_property LEFT 42 [get_bd_ports GPIO_T] +} + + # connections (spi and gpio) + +if {$sys_zynq == 0} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + +} else { + set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] + set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat + + set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] + set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc + + connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] + connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] +} + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] + delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] +} + + # connections (gt) + + connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] + connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] + connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] + connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] + connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] + + # connections (dac) + + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] + + connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] + connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] + connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] + connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] + connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] + connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] + connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] + connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] + connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_pins axi_ad9144_core/dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_pins axi_ad9144_core/dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] + connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + + # connections (adc) + + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] + connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] + connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] + connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] + connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] + connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] + connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core/adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] + connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + + connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] +} + + # gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] +} + + # memory interconnects share the same clock (fclk2) + +if {$sys_zynq == 1} { + set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] + + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] + + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] + connect_bd_net -net sys_fmc_dma_async_reset \ + [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ + [get_bd_pins sys_ps7/FCLK_RESET2_N] + + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source +} + + # interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] +} + + # ila + + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + + set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon + + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm +} + diff --git a/projects/daq2/common/daq2_spi.v b/projects/daq2/common/daq2_spi.v new file mode 100644 index 000000000..eb3e7d91e --- /dev/null +++ b/projects/daq2/common/daq2_spi.v @@ -0,0 +1,109 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module daq2_spi ( + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_sdio); + + // 4 wire + + input [ 2:0] spi_csn; + input spi_clk; + input spi_mosi; + output spi_miso; + + // 3 wire + + inout spi_sdio; + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + IOBUF i_iobuf_sdio ( + .T (spi_enable_s), + .I (spi_mosi), + .O (spi_miso), + .IO (spi_sdio)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq2/kc705/system_bd.tcl b/projects/daq2/kc705/system_bd.tcl new file mode 100644 index 000000000..2e2b96ae9 --- /dev/null +++ b/projects/daq2/kc705/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl +source ../common/daq2_bd.tcl + diff --git a/projects/daq2/kc705/system_constr.xdc b/projects/daq2/kc705/system_constr.xdc new file mode 100644 index 000000000..5a810e137 --- /dev/null +++ b/projects/daq2/kc705/system_constr.xdc @@ -0,0 +1,68 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN E8} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN E7} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN D6} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN D5} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN B6} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN B5} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN A8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN A7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN C8} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN C7} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN D2} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN D1} [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN B2} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN B1} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN A4} [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN A3} [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN G29 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P + +set_property -dict {PACKAGE_PIN G30 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN B25 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] + +set_clock_groups -asynchronous -group {tx_div_clk} +set_clock_groups -asynchronous -group {rx_div_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/daq2/kc705/system_project.tcl b/projects/daq2/kc705/system_project.tcl new file mode 100644 index 000000000..f296237f7 --- /dev/null +++ b/projects/daq2/kc705/system_project.tcl @@ -0,0 +1,16 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create daq2_kc705 +adi_project_files daq2_kc705 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ] + +adi_project_run daq2_kc705 + + diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v new file mode 100644 index 000000000..18ade969c --- /dev/null +++ b/projects/daq2/kc705/system_top.v @@ -0,0 +1,439 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_rst, + sys_clk_p, + sys_clk_n, + + uart_sin, + uart_sout, + + ddr3_1_n, + ddr3_1_p, + ddr3_reset_n, + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ras_n, + ddr3_we_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + + mdio_mdc, + mdio_mdio_io, + mii_rst_n, + mii_col, + mii_crs, + mii_rx_clk, + mii_rx_er, + mii_rx_dv, + mii_rxd, + mii_tx_clk, + mii_tx_en, + mii_txd, + + fan_pwm, + + gpio_lcd, + gpio_led, + gpio_sw, + + iic_rstn, + iic_scl, + iic_sda, + + hdmi_out_clk, + hdmi_hsync, + hdmi_vsync, + hdmi_data_e, + hdmi_data, + + spdif, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_pd, + clkd_sync, + clkd_reset, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio); + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + input uart_sin; + output uart_sout; + + output [ 2:0] ddr3_1_n; + output [ 1:0] ddr3_1_p; + output ddr3_reset_n; + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output ddr3_ras_n; + output ddr3_we_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + + output mdio_mdc; + inout mdio_mdio_io; + output mii_rst_n; + input mii_col; + input mii_crs; + input mii_rx_clk; + input mii_rx_er; + input mii_rx_dv; + input [ 3:0] mii_rxd; + input mii_tx_clk; + output mii_tx_en; + output [ 3:0] mii_txd; + + output fan_pwm; + + inout [ 6:0] gpio_lcd; + inout [ 7:0] gpio_led; + inout [ 8:0] gpio_sw; + + output iic_rstn; + inout iic_scl; + inout iic_sda; + + output hdmi_out_clk; + output hdmi_hsync; + output hdmi_vsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_pd; + inout clkd_sync; + inout clkd_reset; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + + // internal signals + + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire [ 5:0] gpio_ctl_i; + wire [ 5:0] gpio_ctl_o; + wire [ 5:0] gpio_ctl_t; + wire [ 4:0] gpio_status_i; + wire [ 4:0] gpio_status_o; + wire [ 4:0] gpio_status_t; + + // assignments + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + IOBUF i_iobuf_gpio_adc_pd ( + .I (gpio_ctl_o[5]), + .O (gpio_ctl_i[5]), + .T (gpio_ctl_t[5]), + .IO (adc_pd)); + + IOBUF i_iobuf_gpio_dac_txen ( + .I (gpio_ctl_o[4]), + .O (gpio_ctl_i[4]), + .T (gpio_ctl_t[4]), + .IO (dac_txen)); + + IOBUF i_iobuf_gpio_dac_reset ( + .I (gpio_ctl_o[3]), + .O (gpio_ctl_i[3]), + .T (gpio_ctl_t[3]), + .IO (dac_reset)); + + IOBUF i_iobuf_gpio_clkd_pd ( + .I (gpio_ctl_o[2]), + .O (gpio_ctl_i[2]), + .T (gpio_ctl_t[2]), + .IO (clkd_pd)); + + IOBUF i_iobuf_gpio_clkd_sync ( + .I (gpio_ctl_o[1]), + .O (gpio_ctl_i[1]), + .T (gpio_ctl_t[1]), + .IO (clkd_sync)); + + IOBUF i_iobuf_gpio_clkd_reset ( + .I (gpio_ctl_o[0]), + .O (gpio_ctl_i[0]), + .T (gpio_ctl_t[0]), + .IO (clkd_reset)); + + IOBUF i_iobuf_gpio_adc_fdb ( + .I (gpio_status_o[4]), + .O (gpio_status_i[4]), + .T (gpio_status_t[4]), + .IO (adc_fdb)); + + IOBUF i_iobuf_gpio_adc_fda ( + .I (gpio_status_o[3]), + .O (gpio_status_i[3]), + .T (gpio_status_t[3]), + .IO (adc_fda)); + + IOBUF i_iobuf_gpio_dac_irq ( + .I (gpio_status_o[2]), + .O (gpio_status_i[2]), + .T (gpio_status_t[2]), + .IO (dac_irq)); + + IOBUF i_iobuf_gpio_clkd_status_1 ( + .I (gpio_status_o[1]), + .O (gpio_status_i[1]), + .T (gpio_status_t[1]), + .IO (clkd_status[1])); + + IOBUF i_iobuf_gpio_clkd_status_0 ( + .I (gpio_status_o[0]), + .O (gpio_status_i[0]), + .T (gpio_status_t[0]), + .IO (clkd_status[0])); + + system_wrapper i_system_wrapper ( + .ddr3_1_n (ddr3_1_n), + .ddr3_1_p (ddr3_1_p), + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .fan_pwm (fan_pwm), + .gpio_ctl_i (gpio_ctl_i), + .gpio_ctl_o (gpio_ctl_o), + .gpio_ctl_t (gpio_ctl_t), + .gpio_lcd_tri_io (gpio_lcd), + .gpio_led_tri_io (gpio_led), + .gpio_status_i (gpio_status_i), + .gpio_status_o (gpio_status_o), + .gpio_status_t (gpio_status_t), + .gpio_sw_tri_io (gpio_sw), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .iic_rstn (iic_rstn), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio_io), + .mii_col (mii_col), + .mii_crs (mii_crs), + .mii_rst_n (mii_rst_n), + .mii_rx_clk (mii_rx_clk), + .mii_rx_dv (mii_rx_dv), + .mii_rx_er (mii_rx_er), + .mii_rxd (mii_rxd), + .mii_tx_clk (mii_tx_clk), + .mii_tx_en (mii_tx_en), + .mii_txd (mii_txd), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_n (sys_clk_n), + .sys_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .unc_int0 (1'b0), + .unc_int1 (1'b0), + .unc_int4 (1'b0)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl new file mode 100644 index 000000000..c8027e671 --- /dev/null +++ b/projects/daq2/kcu105/system_bd.tcl @@ -0,0 +1,469 @@ + +source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl + + # daq2 + + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_clk_i [create_bd_port -dir I spi_clk_i] + set spi_clk_o [create_bd_port -dir O spi_clk_o] + set spi_sdo_i [create_bd_port -dir I spi_sdo_i] + set spi_sdo_o [create_bd_port -dir O spi_sdo_o] + set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + + set rx_ref_clk [create_bd_port -dir I rx_ref_clk] + set rx_sync [create_bd_port -dir O rx_sync] + set rx_sysref [create_bd_port -dir I rx_sysref] + set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + + set tx_ref_clk [create_bd_port -dir I tx_ref_clk] + set tx_sync [create_bd_port -dir I tx_sync] + set tx_sysref [create_bd_port -dir I tx_sysref] + set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] + set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] + set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] + set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] +} + + # dac peripherals + + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] + set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core + + set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9144_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + + set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma + set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma +} else { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma +} + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +if {$sys_zynq == 1} { + + set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect +} + + # adc peripherals + + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9680_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +} else { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma +} + +if {$sys_zynq == 1} { + + set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect +} + + # dac/adc common gt/gpio + + set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_daq2_gt + +if {$sys_zynq == 1} { + + set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect +} + + # gpio and spi + +if {$sys_zynq == 0} { + + set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_daq2_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + + set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio +} + + # additions to default configuration + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + +} else { + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +} + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect + set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc +} + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 42 [get_bd_ports GPIO_I] + set_property LEFT 42 [get_bd_ports GPIO_O] + set_property LEFT 42 [get_bd_ports GPIO_T] +} + + # connections (spi and gpio) + +if {$sys_zynq == 0} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + +} else { + set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] + set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat + + set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] + set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc + + connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] + connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] +} + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] + delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] +} + + # connections (gt) + + connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] + connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] + connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] + connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] + connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] + + # connections (dac) + + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] + + connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] + connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] + connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] + connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] + connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] + connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] + connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] + connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] + connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_pins axi_ad9144_core/dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_pins axi_ad9144_core/dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] + connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + + # connections (adc) + + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] + connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] + connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] + connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] + connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] + connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] + connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core/adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] + connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_core/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_core/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_spi/s_axi_aresetn] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + + connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] +} + + # gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_cpu_clk_source + connect_bd_net -net sys_cpu_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_cpu_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_daq2_gt/m_axi_aresetn] +} + + # memory interconnects share the same clock (fclk2) + +if {$sys_zynq == 1} { + set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] + + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] + + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] + connect_bd_net -net sys_fmc_dma_async_reset \ + [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ + [get_bd_pins sys_ps7/FCLK_RESET2_N] + + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source +} + + # interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_mem_clk_source + connect_bd_net -net sys_mem_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_mem_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_mem_clk_source + connect_bd_net -net sys_mem_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_resetn_source + connect_bd_net -net sys_cpu_rstn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] +} + + # ila + + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + + set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon + + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_axi_ddr_cntrl + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm +} + diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc new file mode 100644 index 000000000..28c399689 --- /dev/null +++ b/projects/daq2/kcu105/system_constr.xdc @@ -0,0 +1,68 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN H6} [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN H5} [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN E4} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN E3} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN D2} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN D1} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN B2} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN B1} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN A4} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN A3} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN K6} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN K5} [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN F6} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN F5} [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN D6} [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN D5} [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN C4} [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN C3} [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN B6} [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN B5} [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P + +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] + +set_clock_groups -asynchronous -group {tx_div_clk} +set_clock_groups -asynchronous -group {rx_div_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/daq2/kcu105/system_project.tcl b/projects/daq2/kcu105/system_project.tcl new file mode 100644 index 000000000..513f735c5 --- /dev/null +++ b/projects/daq2/kcu105/system_project.tcl @@ -0,0 +1,20 @@ + + +proc use_this_invalid_command_to_crash {} { + + puts "Ignoring timing errors for now!" +} + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create daq2_kcu105 +adi_project_files daq2_kcu105 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] + +adi_project_run daq2_kcu105 + + diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v new file mode 100644 index 000000000..c2bf9eccc --- /dev/null +++ b/projects/daq2/kcu105/system_top.v @@ -0,0 +1,457 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_rst, + sys_clk_p, + sys_clk_n, + sys_125m_clk_p, + sys_125m_clk_n, + + uart_sin, + uart_sout, + + ddr4_act_n, + ddr4_addr, + ddr4_ba, + ddr4_bg, + ddr4_ck_p, + ddr4_ck_n, + ddr4_cke, + ddr4_cs_n, + ddr4_dm_n, + ddr4_dq, + ddr4_dqs_p, + ddr4_dqs_n, + ddr4_odt, + ddr4_par, + ddr4_reset_n, + + mdio_mdc, + mdio_mdio, + phy_rst_n, + phy_rx_p, + phy_rx_n, + phy_tx_p, + phy_tx_n, + + fan_pwm, + pwr_good, + + gpio_led, + gpio_sw, + + iic_rstn, + iic_scl, + iic_sda, + + hdmi_out_clk, + hdmi_hsync, + hdmi_vsync, + hdmi_data_e, + hdmi_data, + + spdif, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_pd, + clkd_sync, + clkd_reset, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio); + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + input sys_125m_clk_p; + input sys_125m_clk_n; + + input uart_sin; + output uart_sout; + + output ddr4_act_n; + output [16:0] ddr4_addr; + output [ 1:0] ddr4_ba; + output [ 0:0] ddr4_bg; + output ddr4_ck_p; + output ddr4_ck_n; + output [ 0:0] ddr4_cke; + output [ 0:0] ddr4_cs_n; + inout [ 7:0] ddr4_dm_n; + inout [63:0] ddr4_dq; + inout [ 7:0] ddr4_dqs_p; + inout [ 7:0] ddr4_dqs_n; + output [ 0:0] ddr4_odt; + output ddr4_par; + output ddr4_reset_n; + + output mdio_mdc; + inout mdio_mdio; + output phy_rst_n; + input phy_rx_p; + input phy_rx_n; + output phy_tx_p; + output phy_tx_n; + + output fan_pwm; + output pwr_good; + + inout [ 7:0] gpio_led; + inout [ 8:0] gpio_sw; + + output iic_rstn; + inout iic_scl; + inout iic_sda; + + output hdmi_out_clk; + output hdmi_hsync; + output hdmi_vsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_pd; + inout clkd_sync; + inout clkd_reset; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + + // internal registers + + reg [31:0] sys_reset_m = 'd0; + reg sys_cpu_rst = 'd0; + reg sys_cpu_rstn = 'd0; + + // internal signals + + wire mdm_reset; + wire mig_reset; + wire mig_ready; + wire sys_cpu_clk; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire [ 5:0] gpio_ctl_i; + wire [ 5:0] gpio_ctl_o; + wire [ 5:0] gpio_ctl_t; + wire [ 4:0] gpio_status_i; + wire [ 4:0] gpio_status_o; + wire [ 4:0] gpio_status_t; + + // assignments + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // default logic + + assign fan_pwm = 1'b1; + assign pwr_good = 1'b1; + + // assign sys_reset_req = mdm_reset | mig_reset | ~mig_ready; + // assign sys_reset_req = mdm_reset; + assign sys_reset_req = 1'b0; + + always @(posedge sys_cpu_clk) begin + if (sys_reset_req == 1'b1) begin + sys_reset_m <= {32{1'b1}}; + end else begin + sys_reset_m <= {sys_reset_m[30:0], 1'b0}; + end + sys_cpu_rst <= sys_reset_m[31]; + sys_cpu_rstn <= ~sys_reset_m[31]; + end + + // instantiations + + IBUFDS_GTE3 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE3 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + IOBUF i_iobuf_gpio_adc_pd ( + .I (gpio_ctl_o[5]), + .O (gpio_ctl_i[5]), + .T (gpio_ctl_t[5]), + .IO (adc_pd)); + + IOBUF i_iobuf_gpio_dac_txen ( + .I (gpio_ctl_o[4]), + .O (gpio_ctl_i[4]), + .T (gpio_ctl_t[4]), + .IO (dac_txen)); + + IOBUF i_iobuf_gpio_dac_reset ( + .I (gpio_ctl_o[3]), + .O (gpio_ctl_i[3]), + .T (gpio_ctl_t[3]), + .IO (dac_reset)); + + IOBUF i_iobuf_gpio_clkd_pd ( + .I (gpio_ctl_o[2]), + .O (gpio_ctl_i[2]), + .T (gpio_ctl_t[2]), + .IO (clkd_pd)); + + IOBUF i_iobuf_gpio_clkd_sync ( + .I (gpio_ctl_o[1]), + .O (gpio_ctl_i[1]), + .T (gpio_ctl_t[1]), + .IO (clkd_sync)); + + IOBUF i_iobuf_gpio_clkd_reset ( + .I (gpio_ctl_o[0]), + .O (gpio_ctl_i[0]), + .T (gpio_ctl_t[0]), + .IO (clkd_reset)); + + IOBUF i_iobuf_gpio_adc_fdb ( + .I (gpio_status_o[4]), + .O (gpio_status_i[4]), + .T (gpio_status_t[4]), + .IO (adc_fdb)); + + IOBUF i_iobuf_gpio_adc_fda ( + .I (gpio_status_o[3]), + .O (gpio_status_i[3]), + .T (gpio_status_t[3]), + .IO (adc_fda)); + + IOBUF i_iobuf_gpio_dac_irq ( + .I (gpio_status_o[2]), + .O (gpio_status_i[2]), + .T (gpio_status_t[2]), + .IO (dac_irq)); + + IOBUF i_iobuf_gpio_clkd_status_1 ( + .I (gpio_status_o[1]), + .O (gpio_status_i[1]), + .T (gpio_status_t[1]), + .IO (clkd_status[1])); + + IOBUF i_iobuf_gpio_clkd_status_0 ( + .I (gpio_status_o[0]), + .O (gpio_status_i[0]), + .T (gpio_status_t[0]), + .IO (clkd_status[0])); + + system_wrapper i_system_wrapper ( + .c0_ddr4_act_n (ddr4_act_n), + .c0_ddr4_adr (ddr4_addr), + .c0_ddr4_ba (ddr4_ba), + .c0_ddr4_bg (ddr4_bg), + .c0_ddr4_ck_c (ddr4_ck_n), + .c0_ddr4_ck_t (ddr4_ck_p), + .c0_ddr4_cke (ddr4_cke), + .c0_ddr4_cs_n (ddr4_cs_n), + .c0_ddr4_dm_n (ddr4_dm_n), + .c0_ddr4_dq (ddr4_dq), + .c0_ddr4_dqs_c (ddr4_dqs_n), + .c0_ddr4_dqs_t (ddr4_dqs_p), + .c0_ddr4_odt (ddr4_odt), + .c0_ddr4_par (ddr4_par), + .c0_ddr4_reset_n (ddr4_reset_n), + .gpio_ctl_i (gpio_ctl_i), + .gpio_ctl_o (gpio_ctl_o), + .gpio_ctl_t (gpio_ctl_t), + .gpio_lcd_tri_io (), + .gpio_led_tri_io (gpio_led), + .gpio_status_i (gpio_status_i), + .gpio_status_o (gpio_status_o), + .gpio_status_t (gpio_status_t), + .gpio_sw_tri_io (gpio_sw), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .iic_rstn (iic_rstn), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .mdm_reset (mdm_reset), + .mig_ready (mig_ready), + .mig_reset (mig_reset), + .phy_rst_n (phy_rst_n), + .phy_sd (1'b1), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .sys_125m_clk_n (sys_125m_clk_n), + .sys_125m_clk_p (sys_125m_clk_p), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_n (sys_clk_n), + .sys_clk_p (sys_clk_p), + .sys_cpu_clk (sys_cpu_clk), + .sys_cpu_rst (sys_cpu_rst), + .sys_cpu_rstn (sys_cpu_rstn), + .sys_rst (sys_rst), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .unc_int4 (1'b0)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl new file mode 100644 index 000000000..fa00f243b --- /dev/null +++ b/projects/daq2/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/daq2_bd.tcl + diff --git a/projects/daq2/zc706/system_constr.xdc b/projects/daq2/zc706/system_constr.xdc new file mode 100644 index 000000000..c7196e9a8 --- /dev/null +++ b/projects/daq2/zc706/system_constr.xdc @@ -0,0 +1,70 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[0]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[0]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[1]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[1]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P + +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {tx_div_clk} +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl new file mode 100644 index 000000000..8a81752de --- /dev/null +++ b/projects/daq2/zc706/system_project.tcl @@ -0,0 +1,16 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create daq2_zc706 +adi_project_files daq2_zc706 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run daq2_zc706 + + diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v new file mode 100644 index 000000000..889b42ade --- /dev/null +++ b/projects/daq2/zc706/system_top.v @@ -0,0 +1,384 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_pd, + clkd_sync, + clkd_reset, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_pd; + inout clkd_sync; + inout clkd_reset; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + + // internal signals + + wire [42:0] gpio_i; + wire [42:0] gpio_o; + wire [42:0] gpio_t; + + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + + // instantiations + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + IOBUF i_iobuf_gpio_adc_pd ( + .I (gpio_o[42]), + .O (gpio_i[42]), + .T (gpio_t[42]), + .IO (adc_pd)); + + IOBUF i_iobuf_gpio_dac_txen ( + .I (gpio_o[41]), + .O (gpio_i[41]), + .T (gpio_t[41]), + .IO (dac_txen)); + + IOBUF i_iobuf_gpio_dac_reset ( + .I (gpio_o[40]), + .O (gpio_i[40]), + .T (gpio_t[40]), + .IO (dac_reset)); + + IOBUF i_iobuf_gpio_clkd_pd ( + .I (gpio_o[39]), + .O (gpio_i[39]), + .T (gpio_t[39]), + .IO (clkd_pd)); + + IOBUF i_iobuf_gpio_clkd_sync ( + .I (gpio_o[38]), + .O (gpio_i[38]), + .T (gpio_t[38]), + .IO (clkd_sync)); + + IOBUF i_iobuf_gpio_clkd_reset ( + .I (gpio_o[37]), + .O (gpio_i[37]), + .T (gpio_t[37]), + .IO (clkd_reset)); + + IOBUF i_iobuf_gpio_adc_fdb ( + .I (gpio_o[36]), + .O (gpio_i[36]), + .T (gpio_t[36]), + .IO (adc_fdb)); + + IOBUF i_iobuf_gpio_adc_fda ( + .I (gpio_o[35]), + .O (gpio_i[35]), + .T (gpio_t[35]), + .IO (adc_fda)); + + IOBUF i_iobuf_gpio_dac_irq ( + .I (gpio_o[34]), + .O (gpio_i[34]), + .T (gpio_t[34]), + .IO (dac_irq)); + + IOBUF i_iobuf_gpio_clkd_status_1 ( + .I (gpio_o[33]), + .O (gpio_i[33]), + .T (gpio_t[33]), + .IO (clkd_status[1])); + + IOBUF i_iobuf_gpio_clkd_status_0 ( + .I (gpio_o[32]), + .O (gpio_i[32]), + .T (gpio_t[32]), + .IO (clkd_status[0])); + + genvar n; + generate + for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref)); + +endmodule + +// *************************************************************************** +// ***************************************************************************