diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index be3a0702d..dd3e2adc1 100644 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -42,94 +42,94 @@ module axi_mc_controller parameter C_S_AXI_MIN_SIZE = 32'hffff ) ( - input ref_clk, // 100 MHz - input ctrl_data_clk, + input ref_clk, // 100 MHz + input ctrl_data_clk, // physical interface - input fmc_m1_fault_i, - output fmc_m1_en_o, - output pwm_ah_o, - output pwm_al_o, - output pwm_bh_o, - output pwm_bl_o, - output pwm_ch_o, - output pwm_cl_o, - output [7:0] gpo_o, + input fmc_m1_fault_i, + output fmc_m1_en_o, + output pwm_ah_o, + output pwm_al_o, + output pwm_bh_o, + output pwm_bl_o, + output pwm_ch_o, + output pwm_cl_o, + output [7:0] gpo_o, // controller connections - input pwm_a_i, - input pwm_b_i, - input pwm_c_i, - input ctrl_data_valid_i, - input [31:0] ctrl_data0_i, - input [31:0] ctrl_data1_i, - input [31:0] ctrl_data2_i, - input [31:0] ctrl_data3_i, - input [31:0] ctrl_data4_i, - input [31:0] ctrl_data5_i, - input [31:0] ctrl_data6_i, - input [31:0] ctrl_data7_i, + input pwm_a_i, + input pwm_b_i, + input pwm_c_i, + input ctrl_data_valid_i, + input [31:0] ctrl_data0_i, + input [31:0] ctrl_data1_i, + input [31:0] ctrl_data2_i, + input [31:0] ctrl_data3_i, + input [31:0] ctrl_data4_i, + input [31:0] ctrl_data5_i, + input [31:0] ctrl_data6_i, + input [31:0] ctrl_data7_i, // interconnection with other modules - output [1:0] sensors_o, - input [2:0] position_i, + output[1:0] sensors_o, + input [2:0] position_i, // dma interface - output adc_clk_o, - input adc_dovf_i, - input adc_dunf_i, - output adc_enable_c0, - output adc_enable_c1, - output adc_enable_c2, - output adc_enable_c3, - output adc_enable_c4, - output adc_enable_c5, - output adc_enable_c6, - output adc_enable_c7, - - output adc_valid_c0, - output adc_valid_c1, - output adc_valid_c2, - output adc_valid_c3, - output adc_valid_c4, - output adc_valid_c5, - output adc_valid_c6, - output adc_valid_c7, - - output [31:0] adc_data_c0, - output [31:0] adc_data_c1, - output [31:0] adc_data_c2, - output [31:0] adc_data_c3, - output [31:0] adc_data_c4, - output [31:0] adc_data_c5, - output [31:0] adc_data_c6, - output [31:0] adc_data_c7, + output adc_clk_o, + input adc_dovf_i, + input adc_dunf_i, + output adc_enable_c0, + output adc_enable_c1, + output adc_enable_c2, + output adc_enable_c3, + output adc_enable_c4, + output adc_enable_c5, + output adc_enable_c6, + output adc_enable_c7, + + output adc_valid_c0, + output adc_valid_c1, + output adc_valid_c2, + output adc_valid_c3, + output adc_valid_c4, + output adc_valid_c5, + output adc_valid_c6, + output adc_valid_c7, + + output [31:0] adc_data_c0, + output [31:0] adc_data_c1, + output [31:0] adc_data_c2, + output [31:0] adc_data_c3, + output [31:0] adc_data_c4, + output [31:0] adc_data_c5, + output [31:0] adc_data_c6, + output [31:0] adc_data_c7, // axi interface - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [31:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [31:0] s_axi_araddr, - output s_axi_arready, - output s_axi_rvalid, - output [1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - input s_axi_rready + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready ); //------------------------------------------------------------------------------ @@ -140,7 +140,8 @@ module axi_mc_controller reg adc_valid = 'd0; reg [31:0] adc_data = 'd0; reg [31:0] up_rdata = 'd0; -reg up_ack = 'd0; +reg up_wack = 'd0; +reg up_rack = 'd0; reg pwm_gen_clk = 'd0; reg one_chan_reg = 'd0; @@ -155,9 +156,10 @@ wire up_clk; // internal signals -wire up_sel_s; -wire up_wr_s; -wire [13:0] up_addr_s; +wire up_rreq_s; +wire up_wreq_s; +wire [13:0] up_raddr_s; +wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; wire [31:0] up_adc_common_rdata_s; wire [31:0] up_control_rdata_s; @@ -169,16 +171,26 @@ wire [31:0] rdata_c4_s; wire [31:0] rdata_c5_s; wire [31:0] rdata_c6_s; wire [31:0] rdata_c7_s; -wire up_adc_common_ack_s; -wire up_control_ack_s; -wire ack_c0_s; -wire ack_c1_s; -wire ack_c2_s; -wire ack_c3_s; -wire ack_c4_s; -wire ack_c5_s; -wire ack_c6_s; -wire ack_c7_s; +wire up_adc_common_wack_s; +wire up_adc_common_rack_s; +wire up_control_wack_s; +wire up_control_rack_s; +wire wack_c0_s; +wire rack_c0_s; +wire wack_c1_s; +wire rack_c1_s; +wire wack_c2_s; +wire rack_c2_s; +wire wack_c3_s; +wire rack_c3_s; +wire wack_c4_s; +wire rack_c4_s; +wire wack_c5_s; +wire rack_c5_s; +wire wack_c6_s; +wire rack_c6_s; +wire wack_c7_s; +wire rack_c7_s; wire run_s; wire star_delta_s; wire dir_s; @@ -187,14 +199,14 @@ wire [10:0] pwm_s; wire [10:0] gpo_s; -wire dpwm_ah_s; -wire dpwm_al_s; -wire dpwm_bh_s; -wire dpwm_bl_s; -wire dpwm_ch_s; -wire dpwm_cl_s; +wire dpwm_ah_s; +wire dpwm_al_s; +wire dpwm_bh_s; +wire dpwm_bl_s; +wire dpwm_ch_s; +wire dpwm_cl_s; -wire foc_ctrl_s; +wire foc_ctrl_s; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- @@ -207,23 +219,23 @@ assign up_rstn = s_axi_aresetn; assign adc_clk_o = ctrl_data_clk; -assign adc_valid_c0 = ctrl_data_valid_i; -assign adc_valid_c1 = ctrl_data_valid_i; -assign adc_valid_c2 = ctrl_data_valid_i; -assign adc_valid_c3 = ctrl_data_valid_i; -assign adc_valid_c4 = ctrl_data_valid_i; -assign adc_valid_c5 = ctrl_data_valid_i; -assign adc_valid_c6 = ctrl_data_valid_i; -assign adc_valid_c7 = ctrl_data_valid_i; +assign adc_valid_c0 = ctrl_data_valid_i; +assign adc_valid_c1 = ctrl_data_valid_i; +assign adc_valid_c2 = ctrl_data_valid_i; +assign adc_valid_c3 = ctrl_data_valid_i; +assign adc_valid_c4 = ctrl_data_valid_i; +assign adc_valid_c5 = ctrl_data_valid_i; +assign adc_valid_c6 = ctrl_data_valid_i; +assign adc_valid_c7 = ctrl_data_valid_i; -assign adc_data_c0 = ctrl_data0_i; -assign adc_data_c1 = ctrl_data1_i; -assign adc_data_c2 = ctrl_data2_i; -assign adc_data_c3 = ctrl_data3_i; -assign adc_data_c4 = ctrl_data4_i; -assign adc_data_c5 = ctrl_data5_i; -assign adc_data_c6 = ctrl_data6_i; -assign adc_data_c7 = ctrl_data7_i; +assign adc_data_c0 = ctrl_data0_i; +assign adc_data_c1 = ctrl_data1_i; +assign adc_data_c2 = ctrl_data2_i; +assign adc_data_c3 = ctrl_data3_i; +assign adc_data_c4 = ctrl_data4_i; +assign adc_data_c5 = ctrl_data5_i; +assign adc_data_c6 = ctrl_data6_i; +assign adc_data_c7 = ctrl_data7_i; assign ctrl_rst_o = !run_s; @@ -258,10 +270,12 @@ end always @(negedge up_rstn or posedge up_clk) begin if(up_rstn == 0) begin up_rdata <= 'd0; - up_ack <= 'd0; + up_wack <= 'd0; + up_rack <= 'd0; end else begin up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s; - up_ack <= up_control_ack_s | up_adc_common_ack_s | ack_c0_s | ack_c1_s | ack_c2_s | ack_c3_s | ack_c4_s | ack_c5_s | ack_c6_s | ack_c7_s; + up_rack <= up_control_rack_s | up_adc_common_rack_s | rack_c0_s | rack_c1_s | rack_c2_s | rack_c3_s | rack_c4_s | rack_c5_s | rack_c6_s | rack_c7_s; + up_wack <= up_control_wack_s | up_adc_common_wack_s | wack_c0_s | wack_c1_s | wack_c2_s | wack_c3_s | wack_c4_s | wack_c5_s | wack_c6_s | wack_c7_s; end end @@ -288,30 +302,32 @@ motor_driver_inst( control_registers control_reg_inst( .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(up_control_rdata_s), - .up_ack(up_control_ack_s), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_control_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_control_rdata_s), + .up_rack (up_control_rack_s), .run_o(run_s), .break_o(), .dir_o(dir_s), .star_delta_o(star_delta_s), .sensors_o(sensors_o), - .kp_o(kp_o), - .ki_o(ki_o), - .kd_o(kd_o), + .kp_o(), + .ki_o(), + .kd_o(), .kp1_o(), .ki1_o(), .kd1_o(), .gpo_o(gpo_s), - .reference_speed_o(ref_speed_o), + .reference_speed_o(), .oloop_matlab_o(foc_ctrl_s), - .err_i(err_i), + .err_i(), .calibrate_adcs_o(), - .pwm_open_o( pwm_open_s)); + .pwm_open_o(pwm_open_s)); up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( .adc_clk(ref_clk), @@ -326,6 +342,8 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -348,12 +366,14 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c0_s), - .up_ack(ack_c0_s)); + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c0_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c0_s), + .up_rack (rack_c0_s)); up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( .adc_clk(ref_clk), @@ -368,6 +388,8 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -390,13 +412,15 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c1_s), - .up_ack(ack_c1_s)); - + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c1_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c1_s), + .up_rack (rack_c1_s)); + up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( .adc_clk(ref_clk), .adc_rst(adc_rst), @@ -410,6 +434,8 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -432,12 +458,14 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c2_s), - .up_ack(ack_c2_s)); + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c2_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c2_s), + .up_rack (rack_c2_s)); up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( .adc_clk(ref_clk), @@ -452,6 +480,8 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -474,12 +504,14 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c3_s), - .up_ack(ack_c3_s)); + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c3_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c3_s), + .up_rack (rack_c3_s)); up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( .adc_clk(ref_clk), @@ -494,6 +526,8 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -516,13 +550,15 @@ up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c4_s), - .up_ack(ack_c4_s)); - + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c4_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c4_s), + .up_rack (rack_c4_s)); + up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( .adc_clk(ref_clk), .adc_rst(adc_rst), @@ -536,6 +572,8 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -558,12 +596,14 @@ up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c5_s), - .up_ack(ack_c5_s)); + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c5_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c5_s), + .up_rack (rack_c5_s)); up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( .adc_clk(ref_clk), @@ -578,6 +618,8 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -600,13 +642,15 @@ up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c6_s), - .up_ack(ack_c6_s)); - + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c6_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c6_s), + .up_rack (rack_c6_s)); + up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7( .adc_clk(ref_clk), .adc_rst(adc_rst), @@ -620,6 +664,8 @@ up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7( .adc_dcfilt_coeff(), .adc_iqcor_coeff_1(), .adc_iqcor_coeff_2(), + .adc_pnseq_sel(), + .adc_data_sel(), .adc_pn_err(1'b0), .adc_pn_oos(1'b0), .adc_or(1'b0), @@ -642,13 +688,15 @@ up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7( .adc_usr_decimation_n(16'd1), .up_rstn(up_rstn), .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(rdata_c7_s), - .up_ack(ack_c7_s)); - + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (wack_c7_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (rdata_c7_s), + .up_rack (rack_c7_s)); + // common processor control up_adc_common i_up_adc_common( @@ -659,9 +707,15 @@ up_adc_common i_up_adc_common( .adc_ddr_edgesel(), .adc_pin_mode(), .adc_status(1'b1), + .adc_sync_status(1'b0), .adc_status_ovf(adc_dovf_i), .adc_status_unf(adc_dunf_i), .adc_clk_ratio(32'd1), + .adc_start_code(), + .adc_sync(), + .up_status_pn_err(1'b0), + .up_status_pn_oos(1'b0), + .up_status_or(1'b0), .delay_clk(1'b0), .delay_rst(), .delay_sel(), @@ -682,14 +736,18 @@ up_adc_common i_up_adc_common( .drp_locked(1'b0), .up_usr_chanmax(), .adc_usr_chanmax(8'd0), - .up_rstn(up_rstn), - .up_clk(up_clk), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(up_adc_common_rdata_s), - .up_ack(up_adc_common_ack_s)); + .up_adc_gpio_in(32'h0), + .up_adc_gpio_out(), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_adc_common_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_adc_common_rdata_s), + .up_rack (up_adc_common_rack_s)); // up bus interface @@ -713,12 +771,14 @@ up_axi i_up_axi( .up_axi_rresp(s_axi_rresp), .up_axi_rdata(s_axi_rdata), .up_axi_rready(s_axi_rready), - .up_sel(up_sel_s), - .up_wr(up_wr_s), - .up_addr(up_addr_s), - .up_wdata(up_wdata_s), - .up_rdata(up_rdata), - .up_ack(up_ack)); + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); endmodule diff --git a/library/axi_mc_controller/control_registers.v b/library/axi_mc_controller/control_registers.v index 7810d0eb1..f8a831c53 100644 --- a/library/axi_mc_controller/control_registers.v +++ b/library/axi_mc_controller/control_registers.v @@ -42,17 +42,19 @@ module control_registers input up_rstn, input up_clk, - input up_sel, - input up_wr, - input [13:0] up_addr, + input up_wreq, + input [13:0] up_waddr, input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, output reg [31:0] up_rdata, - output reg up_ack, + output reg up_rack, //control input [31:0] err_i, - output [31:0] pwm_open_o, + output [10:0] pwm_open_o, output [31:0] reference_speed_o, output [31:0] kp_o, output [31:0] ki_o, @@ -96,15 +98,15 @@ reg [10:0] gpo_r; //internal signals -wire up_sel_s; -wire up_wr_s; +wire up_wreq_s; +wire up_rreq_s; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ -assign up_sel_s = (up_addr[13:4] == 10'h00) ? up_sel : 1'b0; -assign up_wr_s = up_sel_s & up_wr; +assign up_wreq_s = (up_waddr[13:4] == 10'h00) ? up_wreq : 1'b0; +assign up_rreq_s = (up_raddr[13:4] == 10'h00) ? up_rreq : 1'b0; assign run_o = control_r[0]; // Run the motor assign break_o = control_r[2]; // Activate the Break circuit @@ -115,7 +117,7 @@ assign calibrate_adcs_o = control_r[16]; assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1] assign gpo_o = control_r[30:20]; -assign pwm_open_o = pwm_open_r; // PWM value, for open loop control +assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control assign reference_speed_o = reference_speed_r; assign kp_o = kp_r; // KP controller parameter assign ki_o = ki_r; // KI controller parameter @@ -130,6 +132,7 @@ always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin + up_wack <= 1'b0; control_r <= 'h0; reference_speed_r <= 'd1000; kp_r <= 'd6554; @@ -144,51 +147,52 @@ begin end else begin - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h3)) + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h3)) begin reserved_r1 <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin control_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin reference_speed_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin kp_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h7)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin ki_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin kd_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h9)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin kp1_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'ha)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin ki1_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hb)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin kd1_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hc)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin pwm_open_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'hd)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hd)) begin pwm_break_r <= up_wdata; end - if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'he)) + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'he)) begin status_r <= up_wdata; end @@ -200,14 +204,14 @@ end always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin - up_ack <= 'd0; + up_rack <= 'd0; up_rdata <= 'd0; end else begin - up_ack <= up_sel_s; - if (up_sel_s == 1'b1) begin - case (up_addr[3:0]) + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[3:0]) 4'h3: up_rdata <= reserved_r1; 4'h4: up_rdata <= control_r; 4'h5: up_rdata <= reference_speed_r;