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jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface

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Laszlo Nagy 2021-10-22 14:58:57 +01:00 committed by Laszlo Nagy
parent 1d951cfbae
commit 7e5a638386
2 changed files with 18 additions and 0 deletions
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10
library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
View File

@ -65,4 +65,14 @@ adi_add_bus "RX" "master" \
{ "rx_block_sync" "rxblock_sync" } \
}
adi_add_bus "RX_GT_IP_Interface" "master" \
"xilinx.com:interface:gt_rx_interface_rtl:1.0" \
"xilinx.com:interface:gt_rx_interface:1.0" \
{ \
{ "rxdata" "ch_rxdata" } \
{ "rxheader" "ch_rxheader" } \
{ "rxheadervalid" "ch_rxheadervalid" } \
{ "rxgearboxslip" "ch_rxgearboxslip" } \
}
ipx::save_core [ipx::current_core]

8
library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
View File

@ -55,6 +55,14 @@ adi_ip_properties_lite jesd204_versal_gt_adapter_tx
set_property display_name "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
set_property description "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
adi_add_bus "TX_GT_IP_Interface" "master" \
"xilinx.com:interface:gt_tx_interface_rtl:1.0" \
"xilinx.com:interface:gt_tx_interface:1.0" \
{ \
{ "txdata" "ch_txdata" } \
{ "txheader" "ch_txheader" } \
}
adi_add_bus "TX" "slave" \
"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \