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daq1: Add support for A10GX

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Istvan Csomortani 2016-10-24 10:59:07 +03:00
parent de0c487195
commit 7e57a89ce5
7 changed files with 628 additions and 0 deletions
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3
projects/daq1/Makefile
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@ -7,14 +7,17 @@
.PHONY: all clean clean-all
all:
-make -C a10gx all
-make -C zc706 all
clean:
make -C a10gx clean
make -C zc706 clean
clean-all:
make -C a10gx clean-all
make -C zc706 clean-all
####################################################################################

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projects/daq1/a10gx/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
ifeq ($(MMU),)
MMU := 1
endif
export ALT_NIOS_MMU_ENABLED := $(MMU)
M_DEPS += system_top.v
M_DEPS += system_qsys.tcl
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../common/daq1_qsys.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_DEPS += ../../../library/xilinx/common/ad_mmcm_drp.v
M_DEPS += ../../../library/xilinx/common/ad_mul.v
M_DEPS += ../../../library/xilinx/common/ad_serdes_clk.v
M_DEPS += ../../../library/xilinx/common/ad_serdes_in.v
M_DEPS += ../../../library/xilinx/common/ad_serdes_out.v
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: daq1_a10gx.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
daq1_a10gx.sof: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> daq1_a10gx_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/daq1/a10gx/system_constr.sdc Normal file
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "2.000 ns" -name rx_clk_500mhz [get_ports {adc_clk_in}]
create_clock -period "2.000 ns" -name tx_clk_500mhz [get_ports {dac_clk_in}]
derive_pll_clocks
derive_clock_uncertainty

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projects/daq1/a10gx/system_project.tcl Normal file
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load_package flow
source ../../scripts/adi_env.tcl
project_new daq1_a10gx -overwrite
source "../../common/a10gx/a10gx_system_assign.tcl"
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# physical interface
set_location_assignment PIN_AC28 -to dac_clk_in ; ## G02 FMC_LPC_CLK1_M2C_P
set_location_assignment PIN_AD28 -to "dac_clk_in(n)" ; ## G03 FMC_LPC_CLK1_M2C_N
set_location_assignment PIN_AF29 -to dac_clk_out ; ## G27 FMC_LPC_LA25_P
set_location_assignment PIN_AG29 -to "dac_clk_out(n)" ; ## G28 FMC_LPC_LA25_N
set_location_assignment PIN_Y26 -to dac_frame_out ; ## H37 FMC_LPC_LA32_P
set_location_assignment PIN_Y27 -to "dac_frame_out(n)" ; ## H38 FMC_LPC_LA32_N
set_location_assignment PIN_AB15 -to dac_data_out[0] ; ## H19 FMC_LPC_LA15_P
set_location_assignment PIN_AB14 -to "dac_data_out[0](n)" ; ## H20 FMC_LPC_LA15_N
set_location_assignment PIN_AG26 -to dac_data_out[1] ; ## G21 FMC_LPC_LA20_P
set_location_assignment PIN_AG27 -to "dac_data_out[1](n)" ; ## G22 FMC_LPC_LA20_N
set_location_assignment PIN_AH26 -to dac_data_out[2] ; ## H22 FMC_LPC_LA19_P
set_location_assignment PIN_AH27 -to "dac_data_out[2](n)" ; ## H23 FMC_LPC_LA19_N
set_location_assignment PIN_AB27 -to dac_data_out[3] ; ## D20 FMC_LPC_LA17_CC_P
set_location_assignment PIN_AC27 -to "dac_data_out[3](n)" ; ## D21 FMC_LPC_LA17_CC_N
set_location_assignment PIN_AJ26 -to dac_data_out[4] ; ## D23 FMC_LPC_LA23_P
set_location_assignment PIN_AK26 -to "dac_data_out[4](n)" ; ## D24 FMC_LPC_LA23_N
set_location_assignment PIN_AK27 -to dac_data_out[5] ; ## G24 FMC_LPC_LA22_P
set_location_assignment PIN_AK28 -to "dac_data_out[5](n)" ; ## G25 FMC_LPC_LA22_N
set_location_assignment PIN_AE27 -to dac_data_out[6] ; ## C22 FMC_LPC_LA18_CC_P
set_location_assignment PIN_AF27 -to "dac_data_out[6](n)" ; ## C23 FMC_LPC_LA18_CC_N
set_location_assignment PIN_AH28 -to dac_data_out[7] ; ## H25 FMC_LPC_LA21_P
set_location_assignment PIN_AH29 -to "dac_data_out[7](n)" ; ## H26 FMC_LPC_LA21_N
set_location_assignment PIN_AJ30 -to dac_data_out[8] ; ## D26 FMC_LPC_LA26_P
set_location_assignment PIN_AK30 -to "dac_data_out[8](n)" ; ## D27 FMC_LPC_LA26_N
set_location_assignment PIN_AF30 -to dac_data_out[9] ; ## H28 FMC_LPC_LA24_P
set_location_assignment PIN_AG30 -to "dac_data_out[9](n)" ; ## H29 FMC_LPC_LA24_N
set_location_assignment PIN_AJ28 -to dac_data_out[10] ; ## C26 FMC_LPC_LA27_P
set_location_assignment PIN_AJ29 -to "dac_data_out[10](n)" ; ## C27 FMC_LPC_LA27_N
set_location_assignment PIN_AE25 -to dac_data_out[11] ; ## G30 FMC_LPC_LA29_P
set_location_assignment PIN_AF25 -to "dac_data_out[11](n)" ; ## G31 FMC_LPC_LA29_N
set_location_assignment PIN_AD25 -to dac_data_out[12] ; ## H31 FMC_LPC_LA28_P
set_location_assignment PIN_AE26 -to "dac_data_out[12](n)" ; ## H32 FMC_LPC_LA28_N
set_location_assignment PIN_AC29 -to dac_data_out[13] ; ## G33 FMC_LPC_LA31_P
set_location_assignment PIN_AD29 -to "dac_data_out[13](n)" ; ## G34 FMC_LPC_LA31_N
set_location_assignment PIN_AB29 -to dac_data_out[14] ; ## H34 FMC_LPC_LA30_P
set_location_assignment PIN_AB30 -to "dac_data_out[14](n)" ; ## H35 FMC_LPC_LA30_N
set_location_assignment PIN_Y30 -to dac_data_out[15] ; ## G36 FMC_LPC_LA33_P
set_location_assignment PIN_AA30 -to "dac_data_out[15](n)" ; ## G37 FMC_LPC_LA33_N
set_location_assignment PIN_AE13 -to adc_clk_in ; ## G06 FMC_LPC_LA00_CC_P
set_location_assignment PIN_AF13 -to "adc_clk_in(n)" ; ## G07 FMC_LPC_LA00_CC_N
set_location_assignment PIN_AC14 -to adc_data_in[0] ; ## C14 FMC_LPC_LA10_P
set_location_assignment PIN_AC13 -to "adc_data_in[0](n)" ; ## C15 FMC_LPC_LA10_N
set_location_assignment PIN_AF18 -to adc_data_in[1] ; ## C18 FMC_LPC_LA14_P
set_location_assignment PIN_AF17 -to "adc_data_in[1](n)" ; ## C19 FMC_LPC_LA14_N
set_location_assignment PIN_AH17 -to adc_data_in[2] ; ## D17 FMC_LPC_LA13_P
set_location_assignment PIN_AH16 -to "adc_data_in[2](n)" ; ## D18 FMC_LPC_LA13_N
set_location_assignment PIN_AJ16 -to adc_data_in[3] ; ## H16 FMC_LPC_LA11_P
set_location_assignment PIN_AK16 -to "adc_data_in[3](n)" ; ## H17 FMC_LPC_LA11_N
set_location_assignment PIN_AD16 -to adc_data_in[4] ; ## G15 FMC_LPC_LA12_P
set_location_assignment PIN_AD15 -to "adc_data_in[4](n)" ; ## G16 FMC_LPC_LA12_N
set_location_assignment PIN_AH14 -to adc_data_in[5] ; ## D14 FMC_LPC_LA09_P
set_location_assignment PIN_AH13 -to "adc_data_in[5](n)" ; ## D15 FMC_LPC_LA09_N
set_location_assignment PIN_AA15 -to adc_data_in[6] ; ## H13 FMC_LPC_LA07_P
set_location_assignment PIN_AA14 -to "adc_data_in[6](n)" ; ## H14 FMC_LPC_LA07_N
set_location_assignment PIN_AD14 -to adc_data_in[7] ; ## G12 FMC_LPC_LA08_P
set_location_assignment PIN_AD13 -to "adc_data_in[7](n)" ; ## G13 FMC_LPC_LA08_N
set_location_assignment PIN_AE16 -to adc_data_in[8] ; ## D11 FMC_LPC_LA05_P
set_location_assignment PIN_AE15 -to "adc_data_in[8](n)" ; ## D12 FMC_LPC_LA05_N
set_location_assignment PIN_AJ15 -to adc_data_in[9] ; ## H10 FMC_LPC_LA04_P
set_location_assignment PIN_AK15 -to "adc_data_in[9](n)" ; ## H11 FMC_LPC_LA04_N
set_location_assignment PIN_AG12 -to adc_data_in[10] ; ## G09 FMC_LPC_LA03_P
set_location_assignment PIN_AH12 -to "adc_data_in[10](n)" ; ## G10 FMC_LPC_LA03_N
set_location_assignment PIN_AB12 -to adc_data_in[11] ; ## C10 FMC_LPC_LA06_P
set_location_assignment PIN_AC12 -to "adc_data_in[11](n)" ; ## C11 FMC_LPC_LA06_N
set_location_assignment PIN_AE12 -to adc_data_in[12] ; ## H07 FMC_LPC_LA02_P
set_location_assignment PIN_AF12 -to "adc_data_in[12](n)" ; ## H08 FMC_LPC_LA02_N
set_location_assignment PIN_AF15 -to adc_data_in[13] ; ## D08 FMC_LPC_LA01_CC_P
set_location_assignment PIN_AG15 -to "adc_data_in[13](n)" ; ## D09 FMC_LPC_LA01_CC_N
set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_in
set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_out
set_instance_assignment -name IO_STANDARD LVDS -to dac_frame_out
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[0]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[1]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[2]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[3]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[4]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[5]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[6]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[7]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[8]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[9]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[10]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[11]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[12]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[13]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[14]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[15]
set_instance_assignment -name IO_STANDARD LVDS -to adc_clk_in
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[0]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[1]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[2]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[3]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[4]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[5]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[6]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[7]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[8]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[9]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[10]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[11]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[12]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[13]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[14]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[15]
# SPI interface
set_location_assignment PIN_AG16 -to spi_csn ; ## H05 FMC_LPC_CLK0_M2C_N
set_location_assignment PIN_AG17 -to spi_clk ; ## H04 FMC_LPC_CLK0_M2C_P
set_location_assignment PIN_AE18 -to spi_sdio ; ## G18 FMC_LPC_LA16_P
set_location_assignment PIN_AE17 -to spi_int ; ## G19 FMC_LPC_LA16_N
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_csn
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_sdio
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_int
execute_flow -compile

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projects/daq1/a10gx/system_qsys.tcl Normal file
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source ../common/daq1_qsys.tcl
save_system "system_bd.qsys"

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projects/daq1/a10gx/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// ddr3
output ddr3_clk_p,
output ddr3_clk_n,
output [ 14:0] ddr3_a,
output [ 2:0] ddr3_ba,
output ddr3_cke,
output ddr3_cs_n,
output ddr3_odt,
output ddr3_reset_n,
output ddr3_we_n,
output ddr3_ras_n,
output ddr3_cas_n,
inout [ 7:0] ddr3_dqs_p,
inout [ 7:0] ddr3_dqs_n,
inout [ 63:0] ddr3_dq,
output [ 7:0] ddr3_dm,
input ddr3_rzq,
input ddr3_ref_clk,
// ethernet
input eth_ref_clk,
input eth_rxd,
output eth_txd,
output eth_mdc,
inout eth_mdio,
output eth_resetn,
input eth_intn,
// board gpio
input [ 10:0] gpio_bd_i,
output [ 15:0] gpio_bd_o,
// daq1 interface
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output dac_frame_out_p,
output dac_frame_out_n,
output [15:0] dac_data_out_p,
output [15:0] dac_data_out_n,
input adc_clk_in_p,
input adc_clk_in_n,
input [13:0] adc_data_in_p,
input [13:0] adc_data_in_n,
output spi_clk,
output spi_csn,
inout spi_sdio,
input spi_int);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire spi_mosi;
wire spi_miso;
// board specific connections
assign eth_resetn = ~eth_reset;
assign eth_mdio_i = eth_mdio;
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
assign ddr3_a[14:12] = 3'd0;
assign gpio_i[31:27] = gpio_o[31:27];
assign gpio_i[26:16] = gpio_bd_i;
assign gpio_i[15: 0] = gpio_o[15:0];
assign gpio_bd_o = gpio_o[15:0];
// instantiations
daq1_spi i_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_rst_reset_n (sys_resetn),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_ref_clk_clk (eth_ref_clk),
.sys_ethernet_reset_reset (eth_reset),
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
.sys_ethernet_sgmii_txp_0 (eth_txd),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.spi_int(spi_int),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p)
);
endmodule
// ***************************************************************************
// ***************************************************************************

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# DAQ1
# DAC core
add_instance axi_ad9122 axi_ad9122 1.0
set_instance_parameter_value axi_ad9122 {ID} {0}
add_connection sys_clk.clk_reset axi_ad9122.s_axi_reset
add_connection sys_clk.clk axi_ad9122.s_axi_clock
add_connection sys_cpu.data_master axi_ad9122.s_axi
# DAC unpack
add_instance util_ad9122_upack util_upack 1.0
set_instance_parameter_value util_ad9122_upack {CHANNEL_DATA_WIDTH} {64}
set_instance_parameter_value util_ad9122_upack {NUM_OF_CHANNELS} {2}
# DAC DMA
add_instance axi_ad9122_dma axi_dmac 1.0
set_instance_parameter_value axi_ad9122_dma {DMA_DATA_WIDTH_DEST} {128}
set_instance_parameter_value axi_ad9122_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_DEST} {2}
set_instance_parameter_value axi_ad9122_dma {DMA_TYPE_SRC} {0}
set_instance_parameter_value axi_ad9122_dma {CYCLIC} {1}
set_instance_parameter_value axi_ad9122_dma {SYNC_TRANSFER_START} {0}
set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_SRC} {0}
set_instance_parameter_value axi_ad9122_dma {AXI_SLICE_DEST} {0}
set_instance_parameter_value axi_ad9122_dma {DMA_LENGTH_WIDTH} {24}
add_connection sys_clk.clk_reset axi_ad9122_dma.s_axi_reset
add_connection sys_clk.clk axi_ad9122_dma.s_axi_clock
add_connection sys_cpu.data_master axi_ad9122_dma.s_axi
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9122_dma.m_src_axi_reset
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9122_dma.m_src_axi_clock
add_connection axi_ad9122_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
add_connection sys_cpu.irq axi_ad9122_dma.interrupt_sender
add_connection sys_clk.clk axi_ad9122_dma.if_fifo_rd_clk
# DAC path
add_connection axi_ad9122.if_dac_div_clk util_ad9122_upack.if_dac_clk
add_connection util_ad9122_upack.if_dac_valid axi_ad9122_dma.if_fifo_rd_en
add_connection util_ad9122_upack.if_dac_data axi_ad9122_dma.if_fifo_rd_dout
add_connection axi_ad9122_dma.if_fifo_rd_underflow axi_ad9122.if_dac_dunf
add_connection util_ad9122_upack.dac_ch_0 axi_ad9122.dac_ch_0
add_connection util_ad9122_upack.dac_ch_1 axi_ad9122.dac_ch_1
# ADC core
add_instance axi_ad9684 axi_ad9684 1.0
set_instance_parameter_value axi_ad9684 {OR_STATUS} {0}
add_connection sys_clk.clk_reset axi_ad9684.s_axi_reset
add_connection sys_clk.clk axi_ad9684.s_axi_clock
add_connection sys_cpu.data_master axi_ad9684.s_axi
# ADC pack
add_instance util_ad9684_cpack util_cpack 1.0
set_instance_parameter_value util_ad9684_cpack {CHANNEL_DATA_WIDTH} {32}
set_instance_parameter_value util_ad9684_cpack {NUM_OF_CHANNELS} {2}
add_connection sys_clk.clk_reset util_ad9684_cpack.if_adc_rst
add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9684_cpack.if_adc_rst
add_connection axi_ad9684.if_adc_clk util_ad9684_cpack.if_adc_clk
add_connection util_ad9684_cpack.adc_ch_0 axi_ad9684.adc_ch_0
add_connection util_ad9684_cpack.adc_ch_1 axi_ad9684.adc_ch_1
# ADC FIFO
add_instance ad9684_adcfifo util_adcfifo 1.0
set_instance_parameter_value ad9684_adcfifo {ADC_DATA_WIDTH} {64}
set_instance_parameter_value ad9684_adcfifo {DMA_DATA_WIDTH} {64}
set_instance_parameter_value ad9684_adcfifo {DMA_ADDRESS_WIDTH} {16}
add_connection sys_clk.clk_reset ad9684_adcfifo.if_adc_rst
add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9684_adcfifo.if_adc_rst
add_connection axi_ad9684.if_adc_clk ad9684_adcfifo.if_adc_clk
add_connection util_ad9684_cpack.if_adc_valid ad9684_adcfifo.if_adc_wr
add_connection util_ad9684_cpack.if_adc_data ad9684_adcfifo.if_adc_wdata
add_connection sys_ddr3_cntrl.emif_usr_clk ad9684_adcfifo.if_dma_clk
# ADC DMA
add_instance axi_ad9684_dma axi_dmac 1.0
set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_SRC} {1}
set_instance_parameter_value axi_ad9684_dma {DMA_TYPE_DEST} {0}
set_instance_parameter_value axi_ad9684_dma {ID} {1}
set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_SRC} {0}
set_instance_parameter_value axi_ad9684_dma {AXI_SLICE_DEST} {0}
set_instance_parameter_value axi_ad9684_dma {DMA_LENGTH_WIDTH} {24}
set_instance_parameter_value axi_ad9684_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value axi_ad9684_dma {FIFO_SIZE} {16}
set_instance_parameter_value axi_ad9684_dma {CYCLIC} {0}
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.if_s_axis_aclk
add_connection ad9684_adcfifo.if_dma_wr axi_ad9684_dma.if_s_axis_valid
add_connection ad9684_adcfifo.if_dma_wdata axi_ad9684_dma.if_s_axis_data
add_connection ad9684_adcfifo.if_dma_wready axi_ad9684_dma.if_s_axis_ready
add_connection ad9684_adcfifo.if_dma_xfer_req axi_ad9684_dma.if_s_axis_xfer_req
add_connection sys_clk.clk_reset axi_ad9684_dma.s_axi_reset
add_connection sys_clk.clk axi_ad9684_dma.s_axi_clock
add_connection sys_cpu.data_master axi_ad9684_dma.s_axi
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9684_dma.m_dest_axi_reset
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9684_dma.m_dest_axi_clock
add_connection axi_ad9684_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
add_connection sys_cpu.irq axi_ad9684_dma.interrupt_sender
# setting interface property
set_interface_property axi_ad9122_device_if EXPORT_OF axi_ad9122.device_if
set_interface_property axi_ad9684_device_if EXPORT_OF axi_ad9684.device_if
# IRQ bridge for the CPLD IRQ signal
add_instance irq_bridge altera_irq_bridge 16.0
set_instance_parameter_value irq_bridge {IRQ_WIDTH} {1}
add_connection sys_clk.clk_reset irq_bridge.clk_reset
add_connection sys_clk.clk irq_bridge.clk
add_connection sys_cpu.irq irq_bridge.sender0_irq
set_interface_property spi_int EXPORT_OF irq_bridge.receiver_irq
# addresses
set_connection_parameter_value sys_cpu.data_master/axi_ad9122.s_axi baseAddress {0x44A00000}
set_connection_parameter_value sys_cpu.data_master/axi_ad9684.s_axi baseAddress {0x44A20000}
set_connection_parameter_value sys_cpu.data_master/axi_ad9122_dma.s_axi baseAddress {0x44A40000}
set_connection_parameter_value sys_cpu.data_master/axi_ad9684_dma.s_axi baseAddress {0x44A60000}
# interrupts
set_connection_parameter_value sys_cpu.irq/irq_bridge.sender0_irq irqNumber {9}
set_connection_parameter_value sys_cpu.irq/axi_ad9122_dma.interrupt_sender irqNumber {10}
set_connection_parameter_value sys_cpu.irq/axi_ad9684_dma.interrupt_sender irqNumber {11}