arradio/c5soc- updated to new framework/16.0
Rejeesh Kutty
parent
12f44ccbcc
commit
7dfa8c599f
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# ad9361
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add_instance axi_ad9361 axi_ad9361 1.0
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set_instance_parameter_value axi_ad9361 {ID} {0}
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set_instance_parameter_value axi_ad9361 {MODE_1R1T} {0}
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set_instance_parameter_value axi_ad9361 {DEVICE_TYPE} {1}
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set_instance_parameter_value axi_ad9361 {TDD_DISABLE} {0}
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set_instance_parameter_value axi_ad9361 {CMOS_OR_LVDS_N} {0}
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set_instance_parameter_value axi_ad9361 {ADC_DATAPATH_DISABLE} {0}
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set_instance_parameter_value axi_ad9361 {DAC_DATAPATH_DISABLE} {0}
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add_interface axi_ad9361_device_if conduit end
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set_interface_property axi_ad9361_device_if EXPORT_OF axi_ad9361.device_if
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add_interface axi_ad9361_up_enable conduit end
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set_interface_property axi_ad9361_up_enable EXPORT_OF axi_ad9361.if_up_enable
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add_interface axi_ad9361_up_txnrx conduit end
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set_interface_property axi_ad9361_up_txnrx EXPORT_OF axi_ad9361.if_up_txnrx
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add_connection axi_ad9361.if_l_clk axi_ad9361.if_clk
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add_connection sys_clk.clk axi_ad9361.if_delay_clk
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add_connection sys_clk.clk axi_ad9361.s_axi_clock
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add_connection sys_clk.clk_reset axi_ad9361.s_axi_reset
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# adc-wfifo & dac-rfifo
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add_instance util_adc_wfifo util_wfifo 1.0
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set_instance_parameter_value util_adc_wfifo {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_adc_wfifo {DIN_DATA_WIDTH} {16}
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set_instance_parameter_value util_adc_wfifo {DOUT_DATA_WIDTH} {16}
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set_instance_parameter_value util_adc_wfifo {DIN_ADDRESS_WIDTH} {5}
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add_connection axi_ad9361.if_l_clk util_adc_wfifo.if_din_clk
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add_connection axi_ad9361.if_rst util_adc_wfifo.if_din_rst
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add_connection sys_dma_clk.clk util_adc_wfifo.if_dout_clk
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add_connection sys_dma_clk.clk_reset util_adc_wfifo.if_dout_rstn
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add_connection axi_ad9361.adc_ch_0 util_adc_wfifo.din_0
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add_connection axi_ad9361.adc_ch_1 util_adc_wfifo.din_1
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add_connection axi_ad9361.adc_ch_2 util_adc_wfifo.din_2
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add_connection axi_ad9361.adc_ch_3 util_adc_wfifo.din_3
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add_connection util_adc_wfifo.if_din_ovf axi_ad9361.if_adc_dovf
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# adc-wfifo & dac-rfifo
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add_instance util_dac_rfifo util_rfifo 1.0
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set_instance_parameter_value util_dac_rfifo {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_dac_rfifo {DIN_DATA_WIDTH} {16}
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set_instance_parameter_value util_dac_rfifo {DOUT_DATA_WIDTH} {16}
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set_instance_parameter_value util_dac_rfifo {DIN_ADDRESS_WIDTH} {5}
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add_connection axi_ad9361.if_l_clk util_dac_rfifo.if_dout_clk
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add_connection axi_ad9361.if_rst util_dac_rfifo.if_dout_rst
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add_connection sys_dma_clk.clk util_dac_rfifo.if_din_clk
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add_connection sys_dma_clk.clk_reset util_dac_rfifo.if_din_rstn
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add_connection util_dac_rfifo.dout_0 axi_ad9361.dac_ch_0
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add_connection util_dac_rfifo.dout_1 axi_ad9361.dac_ch_1
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add_connection util_dac_rfifo.dout_2 axi_ad9361.dac_ch_2
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add_connection util_dac_rfifo.dout_3 axi_ad9361.dac_ch_3
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add_connection util_dac_rfifo.if_dout_unf axi_ad9361.if_dac_dunf
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# adc-pack & dac-unpack
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add_instance util_adc_pack util_cpack 1.0
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set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_adc_pack {CHANNEL_DATA_WIDTH} {16}
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add_connection sys_dma_clk.clk util_adc_pack.if_adc_clk
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add_connection sys_dma_clk.clk_reset util_adc_pack.if_adc_rst
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add_connection util_adc_wfifo.dout_0 util_adc_pack.adc_ch_0
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add_connection util_adc_wfifo.dout_1 util_adc_pack.adc_ch_1
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add_connection util_adc_wfifo.dout_2 util_adc_pack.adc_ch_2
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add_connection util_adc_wfifo.dout_3 util_adc_pack.adc_ch_3
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# adc-pack & dac-unpack
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add_instance util_dac_upack util_upack 1.0
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set_instance_parameter_value util_dac_upack {NUM_OF_CHANNELS} {4}
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set_instance_parameter_value util_dac_upack {CHANNEL_DATA_WIDTH} {16}
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add_connection sys_dma_clk.clk util_dac_upack.if_dac_clk
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add_connection util_dac_upack.dac_ch_0 util_dac_rfifo.din_0
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add_connection util_dac_upack.dac_ch_1 util_dac_rfifo.din_1
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add_connection util_dac_upack.dac_ch_2 util_dac_rfifo.din_2
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add_connection util_dac_upack.dac_ch_3 util_dac_rfifo.din_3
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# adc-dma & dac-dma
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add_instance axi_adc_dma axi_dmac 1.0
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set_instance_parameter_value axi_adc_dma {ID} {0}
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set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1}
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set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1}
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set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1}
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set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1}
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set_instance_parameter_value axi_adc_dma {CYCLIC} {0}
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set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0}
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set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2}
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set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4}
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add_connection sys_clk.clk axi_adc_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
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add_connection sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
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add_connection sys_dma_clk.clk axi_adc_dma.if_fifo_wr_clk
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add_connection util_adc_pack.if_adc_valid axi_adc_dma.if_fifo_wr_en
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add_connection util_adc_pack.if_adc_sync axi_adc_dma.if_fifo_wr_sync
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add_connection util_adc_pack.if_adc_data axi_adc_dma.if_fifo_wr_din
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add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_wfifo.if_dout_ovf
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# adc-dma & dac-dma
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add_instance axi_dac_dma axi_dmac 1.0
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set_instance_parameter_value axi_dac_dma {ID} {0}
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set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0}
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set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1}
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set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1}
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set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1}
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set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0}
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set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0}
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set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0}
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set_instance_parameter_value axi_dac_dma {CYCLIC} {1}
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set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2}
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set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0}
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set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {4}
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add_connection sys_clk.clk axi_dac_dma.s_axi_clock
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add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset
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add_connection sys_dma_clk.clk axi_dac_dma.m_src_axi_clock
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add_connection sys_dma_clk.clk_reset axi_dac_dma.m_src_axi_reset
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add_connection sys_dma_clk.clk axi_dac_dma.if_fifo_rd_clk
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add_connection util_dac_upack.if_dac_valid axi_dac_dma.if_fifo_rd_en
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add_connection axi_dac_dma.if_fifo_rd_dout util_dac_upack.if_dac_data
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add_connection axi_dac_dma.if_fifo_rd_xfer_req util_dac_upack.if_dma_xfer_in
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add_connection axi_dac_dma.if_fifo_rd_underflow util_dac_rfifo.if_din_unf
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# interrupts
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ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender
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ad_cpu_interrupt 3 axi_dac_dma.interrupt_sender
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# cpu interconnects
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ad_cpu_interconnect 0x00120000 axi_ad9361.s_axi
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ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi
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ad_cpu_interconnect 0x00104000 axi_dac_dma.s_axi
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# mem interconnects
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ad_dma_interconnect axi_adc_dma.m_dest_axi 0
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ad_dma_interconnect axi_dac_dma.m_src_axi 1
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package require qsys
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set_module_property NAME {system_bd}
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set_project_property DEVICE_FAMILY {Cyclone V}
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set_project_property DEVICE {5CSXFC6D6F31C8ES}
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# system clock
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add_instance sys_clk clock_source 16.0
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set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
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set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
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set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
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add_interface sys_clk clock sink
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add_interface sys_rst reset sink
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set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
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set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
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# hps
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add_instance sys_hps altera_hps 16.0
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set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
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set_instance_parameter_value sys_hps {F2SDRAM_Type} {Avalon-MM\ Bidirectional AXI-3 AXI-3}
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set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
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set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
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set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
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set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
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set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
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set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
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set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
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set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
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set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
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set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
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set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
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set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
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set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
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set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
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set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
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set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
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set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
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set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
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set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
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set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
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set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
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set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
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set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
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set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
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set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
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set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
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set_instance_parameter_value sys_hps {MEM_TCL} {11}
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set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
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set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
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set_instance_parameter_value sys_hps {MEM_WTCL} {8}
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set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
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set_instance_parameter_value sys_hps {TIMING_TIS} {180}
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set_instance_parameter_value sys_hps {TIMING_TIH} {140}
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set_instance_parameter_value sys_hps {TIMING_TDS} {30}
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set_instance_parameter_value sys_hps {TIMING_TDH} {65}
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set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
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set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
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set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
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set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
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set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
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set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
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set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
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set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
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set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
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set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
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set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
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set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
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set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
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set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
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set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
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set_instance_parameter_value sys_hps {MEM_TWTR} {4}
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set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
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set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
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set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
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set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
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set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
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set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
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set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
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set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
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add_interface sys_hps_memory conduit end
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set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
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add_interface sys_hps_hps_io conduit end
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set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
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add_interface sys_hps_h2f_reset reset source
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set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
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add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
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add_connection sys_clk.clk sys_hps.h2f_axi_clock
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add_connection sys_clk.clk sys_hps.f2h_axi_clock
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add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
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# cpu/hps handling
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proc ad_cpu_interrupt {m_irq m_port} {
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add_connection sys_hps.f2h_irq0 ${m_port}
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set_connection_parameter_value sys_hsp.f2h_irq0/${m_port} irqNumber ${m_irq}
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}
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proc ad_cpu_interconnect {m_base m_port} {
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add_connection sys_hps.h2f_lw_axi_master ${m_port}
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
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}
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proc ad_dma_interconnect {m_port m_id} {
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if {${id} == 1} {
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add_connection ${m_port} sys_hps.f2h_sdram1_data
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set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
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}
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add_connection ${m_port} sys_hps.f2h_sdram2_data
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set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram2_data baseAddress {0x0000}
|
||||
}
|
||||
|
||||
# common dma interfaces
|
||||
|
||||
add_instance sys_dma_clk clock_source 16.0
|
||||
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
|
||||
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
|
||||
add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
|
||||
add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
|
||||
|
||||
# internal memory
|
||||
|
||||
add_instance sys_int_mem altera_avalon_onchip_memory2 16.0
|
||||
set_instance_parameter_value sys_int_mem {dualPort} {0}
|
||||
set_instance_parameter_value sys_int_mem {dataWidth} {64}
|
||||
set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
|
||||
set_instance_parameter_value sys_int_mem {initMemContent} {0}
|
||||
add_connection sys_clk.clk sys_int_mem.clk1
|
||||
add_connection sys_clk.clk_reset sys_int_mem.reset1
|
||||
add_connection sys_hps.h2f_axi_master sys_int_mem.s1
|
||||
set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
|
||||
|
||||
# display (vga-pll)
|
||||
|
||||
add_instance vga_pll altera_pll 16.0
|
||||
set_instance_parameter_value vga_pll {gui_device_speed_grade} {2}
|
||||
set_instance_parameter_value vga_pll {gui_reference_clock_frequency} {50.0}
|
||||
set_instance_parameter_value vga_pll {gui_use_locked} {0}
|
||||
set_instance_parameter_value vga_pll {gui_number_of_clocks} {2}
|
||||
set_instance_parameter_value vga_pll {gui_output_clock_frequency0} {85.5}
|
||||
set_instance_parameter_value vga_pll {gui_output_clock_frequency1} {171.0}
|
||||
add_connection sys_clk.clk vga_pll.refclk
|
||||
add_connection sys_clk.clk_reset vga_pll.reset
|
||||
|
||||
# display (vga-frame-reader)
|
||||
|
||||
add_instance vga_frame_reader alt_vip_vfr 16.0
|
||||
set_instance_parameter_value vga_frame_reader {BITS_PER_PIXEL_PER_COLOR_PLANE} {8}
|
||||
set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_PARALLEL} {4}
|
||||
set_instance_parameter_value vga_frame_reader {NUMBER_OF_CHANNELS_IN_SEQUENCE} {1}
|
||||
set_instance_parameter_value vga_frame_reader {MAX_IMAGE_WIDTH} {1360}
|
||||
set_instance_parameter_value vga_frame_reader {MAX_IMAGE_HEIGHT} {768}
|
||||
set_instance_parameter_value vga_frame_reader {MEM_PORT_WIDTH} {128}
|
||||
set_instance_parameter_value vga_frame_reader {RMASTER_FIFO_DEPTH} {64}
|
||||
set_instance_parameter_value vga_frame_reader {RMASTER_BURST_TARGET} {32}
|
||||
set_instance_parameter_value vga_frame_reader {CLOCKS_ARE_SEPARATE} {1}
|
||||
add_connection sys_clk.clk vga_frame_reader.clock_master
|
||||
add_connection sys_clk.clk_reset vga_frame_reader.clock_master_reset
|
||||
add_connection vga_frame_reader.avalon_master sys_hps.f2h_sdram0_data
|
||||
set_connection_parameter_value vga_frame_reader.avalon_master/sys_hps.f2h_sdram0_data baseAddress {0x0000}
|
||||
add_connection vga_pll.outclk0 vga_frame_reader.clock_reset
|
||||
add_connection sys_clk.clk_reset vga_frame_reader.clock_reset_reset
|
||||
|
||||
# display (vga-out-clock)
|
||||
|
||||
add_instance vga_out_clock altera_clock_bridge 16.0
|
||||
set_instance_parameter_value vga_out_clock {NUM_CLOCK_OUTPUTS} {1}
|
||||
add_connection vga_pll.outclk0 vga_out_clock.in_clk
|
||||
add_interface vga_out_clk clock source
|
||||
set_interface_property vga_out_clk EXPORT_OF vga_out_clock.out_clk
|
||||
|
||||
# display (vga-out-data)
|
||||
|
||||
add_instance vga_out_data alt_vip_itc 14.0
|
||||
set_instance_parameter_value vga_out_data {H_ACTIVE_PIXELS} {1360}
|
||||
set_instance_parameter_value vga_out_data {V_ACTIVE_LINES} {768}
|
||||
set_instance_parameter_value vga_out_data {BPS} {8}
|
||||
set_instance_parameter_value vga_out_data {NUMBER_OF_COLOUR_PLANES} {4}
|
||||
set_instance_parameter_value vga_out_data {COLOUR_PLANES_ARE_IN_PARALLEL} {1}
|
||||
set_instance_parameter_value vga_out_data {ACCEPT_COLOURS_IN_SEQ} {0}
|
||||
set_instance_parameter_value vga_out_data {INTERLACED} {0}
|
||||
set_instance_parameter_value vga_out_data {USE_EMBEDDED_SYNCS} {0}
|
||||
set_instance_parameter_value vga_out_data {AP_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {ANC_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {H_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {V_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {H_SYNC_LENGTH} {112}
|
||||
set_instance_parameter_value vga_out_data {H_FRONT_PORCH} {64}
|
||||
set_instance_parameter_value vga_out_data {H_BACK_PORCH} {256}
|
||||
set_instance_parameter_value vga_out_data {V_SYNC_LENGTH} {6}
|
||||
set_instance_parameter_value vga_out_data {V_FRONT_PORCH} {3}
|
||||
set_instance_parameter_value vga_out_data {V_BACK_PORCH} {18}
|
||||
set_instance_parameter_value vga_out_data {F_RISING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {F_FALLING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_RISING_EDGE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_ANC_LINE} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_BLANK} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_SYNC_LENGTH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_FRONT_PORCH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIELD0_V_BACK_PORCH} {0}
|
||||
set_instance_parameter_value vga_out_data {FIFO_DEPTH} {1920}
|
||||
set_instance_parameter_value vga_out_data {THRESHOLD} {1919}
|
||||
set_instance_parameter_value vga_out_data {CLOCKS_ARE_SAME} {0}
|
||||
set_instance_parameter_value vga_out_data {USE_CONTROL} {0}
|
||||
set_instance_parameter_value vga_out_data {GENERATE_SYNC} {0}
|
||||
set_instance_parameter_value vga_out_data {NO_OF_MODES} {1}
|
||||
set_instance_parameter_value vga_out_data {STD_WIDTH} {1}
|
||||
add_connection vga_pll.outclk0 vga_out_data.is_clk_rst
|
||||
add_connection sys_clk.clk_reset vga_out_data.is_clk_rst_reset
|
||||
add_connection vga_frame_reader.avalon_streaming_source vga_out_data.din
|
||||
add_interface vga_out_data conduit end
|
||||
set_interface_property vga_out_data EXPORT_OF vga_out_data.clocked_video
|
||||
|
||||
# id
|
||||
|
||||
add_instance sys_id altera_avalon_sysid_qsys 16.0
|
||||
set_instance_parameter_value sys_id {id} {-1395322110}
|
||||
add_connection sys_clk.clk sys_id.clk
|
||||
add_connection sys_clk.clk_reset sys_id.reset
|
||||
|
||||
# gpio-bd
|
||||
|
||||
add_instance sys_gpio_bd altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
|
||||
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_bd {width} {32}
|
||||
add_connection sys_clk.clk sys_gpio_bd.clk
|
||||
add_connection sys_clk.clk_reset sys_gpio_bd.reset
|
||||
add_interface sys_gpio_bd conduit end
|
||||
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio.external_connection
|
||||
|
||||
# gpio-in
|
||||
|
||||
add_instance sys_gpio_in altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_in {direction} {Input}
|
||||
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_in {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_in.reset
|
||||
add_connection sys_clk.clk sys_gpio_in.clk
|
||||
add_interface sys_gpio_in conduit end
|
||||
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
||||
|
||||
# gpio-out
|
||||
|
||||
add_instance sys_gpio_out altera_avalon_pio 16.0
|
||||
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
||||
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
||||
set_instance_parameter_value sys_gpio_out {width} {32}
|
||||
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
||||
add_connection sys_clk.clk sys_gpio_out.clk
|
||||
add_interface sys_gpio_out conduit end
|
||||
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
||||
|
||||
# spi
|
||||
|
||||
add_instance sys_spi altera_avalon_spi 16.0
|
||||
set_instance_parameter_value sys_spi {clockPhase} {0}
|
||||
set_instance_parameter_value sys_spi {clockPolarity} {1}
|
||||
set_instance_parameter_value sys_spi {dataWidth} {8}
|
||||
set_instance_parameter_value sys_spi {masterSPI} {1}
|
||||
set_instance_parameter_value sys_spi {numberOfSlaves} {1}
|
||||
set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
|
||||
add_connection sys_clk.clk sys_spi.clk
|
||||
add_connection sys_clk.clk_reset sys_spi.reset
|
||||
add_interface sys_spi conduit end
|
||||
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 0 sys_gpio_bd.irq
|
||||
ad_cpu_interrupt 1 sys_spi.irq
|
||||
ad_cpu_interrupt 4 vga_frame_reader.interrupt_sender
|
||||
|
||||
# cpu interconnects
|
||||
|
||||
ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
|
||||
ad_cpu_interconnect 0x00009000 vga_frame_reader.avalon_slave
|
||||
ad_cpu_interconnect 0x00010000 sys_id.control_slave
|
||||
ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
|
||||
ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
|
||||
ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
|
||||
|
||||
Loading…
Reference in New Issue