diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v new file mode 100644 index 000000000..609dcc226 --- /dev/null +++ b/library/axi_ad9361/axi_ad9361_cmos_if.v @@ -0,0 +1,562 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_cmos_if ( + + // physical interface (receive) + + rx_clk_in, + rx_frame_in, + rx_data_in, + + // physical interface (transmit) + + tx_clk_out, + tx_frame_out, + tx_data_out, + + // ensm control + + enable, + txnrx, + + // clock (common to both receive and transmit) + + rst, + clk, + l_clk, + + // receive data path interface + + adc_valid, + adc_data, + adc_status, + adc_r1_mode, + adc_ddr_edgesel, + + // transmit data path interface + + dac_valid, + dac_data, + dac_r1_mode, + + // tdd interface + + tdd_enable, + tdd_txnrx, + tdd_mode, + + // delay interface + + up_clk, + up_enable, + up_txnrx, + up_adc_dld, + up_adc_dwdata, + up_adc_drdata, + up_dac_dld, + up_dac_dwdata, + up_dac_drdata, + delay_clk, + delay_rst, + delay_locked); + + // this parameter controls the buffer type based on the target device. + + parameter DEVICE_TYPE = 0; + parameter DAC_IODELAY_ENABLE = 0; + parameter IO_DELAY_GROUP = "dev_if_delay_group"; + + // physical interface (receive) + + input rx_clk_in; + input rx_frame_in; + input [11:0] rx_data_in; + + // physical interface (transmit) + + output tx_clk_out; + output tx_frame_out; + output [11:0] tx_data_out; + + // ensm control + + output enable; + output txnrx; + + // clock (common to both receive and transmit) + + input rst; + input clk; + output l_clk; + + // receive data path interface + + output adc_valid; + output [47:0] adc_data; + output adc_status; + input adc_r1_mode; + input adc_ddr_edgesel; + + // transmit data path interface + + input dac_valid; + input [47:0] dac_data; + input dac_r1_mode; + + // tdd interface + + input tdd_enable; + input tdd_txnrx; + input tdd_mode; + + // delay interface + + input up_clk; + input up_enable; + input up_txnrx; + input [12:0] up_adc_dld; + input [64:0] up_adc_dwdata; + output [64:0] up_adc_drdata; + input [15:0] up_dac_dld; + input [79:0] up_dac_dwdata; + output [79:0] up_dac_drdata; + input delay_clk; + input delay_rst; + output delay_locked; + + // internal registers + + reg [ 1:0] rx_frame = 0; + reg [11:0] rx_data_p = 0; + reg rx_error_r1 = 'd0; + reg rx_valid_r1 = 'd0; + reg [23:0] rx_data_r1 = 'd0; + reg rx_error_r2 = 'd0; + reg rx_valid_r2 = 'd0; + reg [47:0] rx_data_r2 = 'd0; + reg adc_p_valid = 'd0; + reg [47:0] adc_p_data = 'd0; + reg adc_p_status = 'd0; + reg adc_n_valid = 'd0; + reg [47:0] adc_n_data = 'd0; + reg adc_n_status = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg adc_valid = 'd0; + reg [47:0] adc_data = 'd0; + reg adc_status = 'd0; + reg [ 1:0] tx_data_cnt = 'd0; + reg [47:0] tx_data = 'd0; + reg tx_frame_p = 'd0; + reg tx_frame_n = 'd0; + reg [11:0] tx_data_p = 'd0; + reg [11:0] tx_data_n = 'd0; + reg tx_n_frame_p = 'd0; + reg tx_n_frame_n = 'd0; + reg [11:0] tx_n_data_p = 'd0; + reg [11:0] tx_n_data_n = 'd0; + reg tx_p_frame_p = 'd0; + reg tx_p_frame_n = 'd0; + reg [11:0] tx_p_data_p = 'd0; + reg [11:0] tx_p_data_n = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_n_int = 'd0; + reg txnrx_n_int = 'd0; + reg enable_p_int = 'd0; + reg txnrx_p_int = 'd0; + + // internal signals + + wire [ 1:0] rx_frame_s; + wire [ 3:0] rx_frame_4_s; + wire [ 2:0] tx_data_sel_s; + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_frame_p_s; + wire rx_frame_n_s; + + genvar l_inst; + + // receive data path interface + + assign rx_frame_s = {rx_frame_p_s, rx_frame_n_s}; + assign rx_frame_4_s = {rx_frame_s, rx_frame}; + + always @(posedge l_clk) begin + rx_frame <= rx_frame_s; + rx_data_p <= rx_data_p_s; + end + + // receive data path for single rf, frame is expected to qualify i only + + always @(posedge l_clk) begin + rx_error_r1 <= ~^ rx_frame_s; + rx_valid_r1 <= ^ rx_frame_s; + case (rx_frame_s) + 2'b01: rx_data_r1 <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r1 <= {rx_data_n_s, rx_data_p}; + default: rx_data_r1 <= 24'd0; + endcase + end + + // receive data path for dual rf, frame is expected to qualify iq for rf-1 only + + always @(posedge l_clk) begin + rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || + (rx_frame_4_s == 4'b1001)) ? 1'b0 : 1'b1; + rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) || + (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0; + case (rx_frame_s) + 2'b11: rx_data_r2[23: 0] <= {rx_data_p_s, rx_data_n_s}; + 2'b01: rx_data_r2[23: 0] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[23: 0] <= rx_data_r2[23: 0]; + endcase + case (rx_frame_s) + 2'b00: rx_data_r2[47:24] <= {rx_data_p_s, rx_data_n_s}; + 2'b10: rx_data_r2[47:24] <= {rx_data_n_s, rx_data_p}; + default: rx_data_r2[47:24] <= rx_data_r2[47:24]; + endcase + end + + // receive data path mux + + always @(posedge l_clk) begin + if (adc_r1_mode == 1'b1) begin + adc_p_valid <= rx_valid_r1; + adc_p_data <= {24'd0, rx_data_r1}; + adc_p_status <= ~rx_error_r1; + end else begin + adc_p_valid <= rx_valid_r2; + adc_p_data <= rx_data_r2; + adc_p_status <= ~rx_error_r2; + end + end + + // transfer to a synchronous common clock + + always @(negedge l_clk) begin + adc_n_valid <= adc_p_valid; + adc_n_data <= adc_p_data; + adc_n_status <= adc_p_status; + end + + always @(posedge clk) begin + adc_valid_int <= adc_n_valid; + adc_data_int <= adc_n_data; + adc_status_int <= adc_n_status; + adc_valid <= adc_valid_int; + if (adc_valid_int == 1'b1) begin + adc_data <= adc_data_int; + end + adc_status <= adc_status_int; + end + + // transmit data path mux (reverse of what receive does above) + // the count simply selets the data muxing on the ddr outputs + + assign tx_data_sel_s = {tx_data_cnt[1], dac_r1_mode, tx_data_cnt[0]}; + + always @(posedge clk) begin + if (dac_valid == 1'b1) begin + tx_data_cnt <= 2'b10; + end else if (tx_data_cnt[1] == 1'b1) begin + tx_data_cnt <= tx_data_cnt + 1'b1; + end + if (dac_valid == 1'b1) begin + tx_data <= dac_data; + end + case (tx_data_sel_s) + 3'b100: begin + tx_frame_p <= 1'b0; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[35:24]; + tx_data_n <= tx_data[47:36]; + end + 3'b101: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b1; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + 3'b110: begin + tx_frame_p <= 1'b1; + tx_frame_n <= 1'b0; + tx_data_p <= tx_data[11: 0]; + tx_data_n <= tx_data[23:12]; + end + default: begin + tx_frame_p <= 1'd0; + tx_frame_n <= 1'd0; + tx_data_p <= 12'd0; + tx_data_n <= 12'd0; + end + endcase + end + + // transfer data from a synchronous clock (skew less than 2ns) + + always @(negedge clk) begin + tx_n_frame_p <= tx_frame_p; + tx_n_frame_n <= tx_frame_n; + tx_n_data_p <= tx_data_p; + tx_n_data_n <= tx_data_n; + end + + always @(posedge l_clk) begin + tx_p_frame_p <= tx_n_frame_p; + tx_p_frame_n <= tx_n_frame_n; + tx_p_data_p <= tx_n_data_p; + tx_p_data_n <= tx_n_data_n; + end + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + always @(negedge clk) begin + enable_n_int <= enable_int; + txnrx_n_int <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_p_int <= enable_n_int; + txnrx_p_int <= txnrx_n_int; + end + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_data ( + .rx_clk (l_clk), + .rx_data_in (rx_data_in[l_inst]), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive frame interface, ibuf -> idelay -> iddr + + ad_cmos_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_frame ( + .rx_clk (l_clk), + .rx_data_in_p (rx_frame_in), + .rx_data_p (rx_frame_p_s), + .rx_data_n (rx_frame_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface, oddr -> obuf + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_data ( + .tx_clk (l_clk), + .tx_data_p (tx_p_data_p[l_inst]), + .tx_data_n (tx_p_data_n[l_inst]), + .tx_data_out (tx_data_out[l_inst]), + .up_clk (up_clk), + .up_dld (up_dac_dld[l_inst]), + .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit frame interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_frame ( + .tx_clk (l_clk), + .tx_data_p (tx_p_frame_p), + .tx_data_n (tx_p_frame_n), + .tx_data_out (tx_frame_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_clk ( + .tx_clk (l_clk), + .tx_data_p (1'b0), + .tx_data_n (1'b1), + .tx_data_out (tx_clk_out), + .up_clk (up_clk), + .up_dld (up_dac_dld[13]), + .up_dwdata (up_dac_dwdata[69:65]), + .up_drdata (up_dac_drdata[69:65]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // enable, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_enable ( + .tx_clk (l_clk), + .tx_data_p (enable_p_int), + .tx_data_n (enable_p_int), + .tx_data_out (enable), + .up_clk (up_clk), + .up_dld (up_dac_dld[14]), + .up_dwdata (up_dac_dwdata[74:70]), + .up_drdata (up_dac_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // txnrx, oddr -> obuf + + ad_cmos_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_txnrx ( + .tx_clk (l_clk), + .tx_data_p (txnrx_p_int), + .tx_data_n (txnrx_p_int), + .tx_data_out (txnrx), + .up_clk (up_clk), + .up_dld (up_dac_dld[15]), + .up_dwdata (up_dac_dwdata[79:75]), + .up_drdata (up_dac_drdata[79:75]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // device clock interface (receive clock) + + ad_cmos_clk #( + .DEVICE_TYPE (DEVICE_TYPE)) + i_clk ( + .clk_in (rx_clk_in), + .clk (l_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/ad_cmos_clk.v b/library/common/ad_cmos_clk.v new file mode 100644 index 000000000..f5a344f65 --- /dev/null +++ b/library/common/ad_cmos_clk.v @@ -0,0 +1,79 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_cmos_clk ( + + clk_in, + clk); + + parameter DEVICE_TYPE = 0; + localparam SERIES7 = 0; + localparam VIRTEX6 = 1; + + input clk_in; + output clk; + + // wires + + wire clk_ibuf_s; + + // instantiations + + IBUFG i_rx_clk_ibuf ( + .I (clk_in), + .O (clk_ibuf_s)); + + generate + if (DEVICE_TYPE == VIRTEX6) begin + BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (clk_ibuf_s), + .O (clk)); + end else begin + BUFG i_clk_gbuf ( + .I (clk_ibuf_s), + .O (clk)); + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/ad_cmos_in.v b/library/common/ad_cmos_in.v new file mode 100644 index 000000000..cf2081778 --- /dev/null +++ b/library/common/ad_cmos_in.v @@ -0,0 +1,196 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_cmos_in ( + + // data interface + + rx_clk, + rx_data_in, + rx_data_p, + rx_data_n, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); + + // parameters + + parameter SINGLE_ENDED = 0; + parameter DEVICE_TYPE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; + localparam SERIES7 = 0; + localparam VIRTEX6 = 1; + + // data interface + + input rx_clk; + input rx_data_in; + output rx_data_p; + output rx_data_n; + + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + + // internal registers + + reg rx_data_n; + + // internal signals + + wire rx_data_n_s; + wire rx_data_ibuf_s; + wire rx_data_idelay_s; + + // delay controller + + generate + if (IODELAY_CTRL == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // receive data interface, ibuf -> idelay -> iddr + + IBUF i_rx_data_ibuf ( + .I (rx_data_in), + .O (rx_data_ibuf_s)); + + generate + if (DEVICE_TYPE == VIRTEX6) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IODELAYE1 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("I"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VAR_LOADABLE"), + .IDELAY_VALUE (0), + .ODELAY_TYPE ("FIXED"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .T (1'b1), + .CE (1'b0), + .INC (1'b0), + .CLKIN (1'b0), + .DATAIN (1'b0), + .ODATAIN (1'b0), + .CINVCTRL (1'b0), + .C (up_clk), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .RST (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end else begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end + endgenerate + + IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .SRTYPE ("ASYNC")) + i_rx_data_iddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n_s)); + + always @(posedge rx_clk) begin + rx_data_n <= rx_data_n_s; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/ad_cmos_out.v b/library/common/ad_cmos_out.v new file mode 100644 index 000000000..9537d6dd1 --- /dev/null +++ b/library/common/ad_cmos_out.v @@ -0,0 +1,164 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_cmos_out ( + + // data interface + + tx_clk, + tx_data_p, + tx_data_n, + tx_data_out, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); + + // parameters + + parameter DEVICE_TYPE = 0; + parameter SINGLE_ENDED = 0; + parameter IODELAY_ENABLE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; + localparam SERIES7 = 0; + localparam VIRTEX6 = 1; + + // data interface + + input tx_clk; + input tx_data_p; + input tx_data_n; + output tx_data_out; + + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + + // internal signals + + wire tx_data_oddr_s; + wire tx_data_odelay_s; + + // delay controller + + generate + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // transmit data interface, oddr -> odelay -> obuf + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("ASYNC")) + i_tx_data_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (tx_clk), + .D1 (tx_data_p), + .D2 (tx_data_n), + .Q (tx_data_oddr_s)); + + generate + if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + ODELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .ODELAY_TYPE ("VAR_LOAD"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_tx_data_odelay ( + .CE (1'b0), + .CLKIN (1'b0), + .INC (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .ODATAIN (tx_data_oddr_s), + .DATAOUT (tx_data_odelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end else begin + assign up_drdata = 5'd0; + assign tx_data_odelay_s = tx_data_oddr_s; + end + endgenerate + + OBUF i_tx_data_obuf ( + .I (tx_data_odelay_s), + .O (tx_data_out)); + +endmodule + +// *************************************************************************** +// ***************************************************************************