axi_ad9361: Update the PPS receiver module
+ Add a HDL parameter for the PPS receiver module : PPS_RECEIVER_ENABLE. By default the module is disabled. + Add the CMOS_OR_LVDS_N and PPS_RECEIVER_ENABLE into the CONFIG register + Define a pps_status read only register, which will be asserted, if the free running counter reach a certain fixed threshold. (2^28) The register can be deasserted by an incomming PPS only.main
Istvan Csomortani
parent
e644a99648
commit
7cdb11cc34
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@ -43,6 +43,7 @@ module axi_ad9361 #(
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parameter MODE_1R1T = 0,
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parameter DEVICE_TYPE = 0,
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parameter TDD_DISABLE = 0,
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parameter PPS_RECEIVER_ENABLE = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter ADC_INIT_DELAY = 0,
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parameter ADC_DATAPATH_DISABLE = 0,
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@ -284,6 +285,7 @@ module axi_ad9361 #(
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wire up_drp_locked;
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wire [31:0] up_pps_rcounter_s;
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wire up_pps_status_s;
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wire up_irq_mask_s;
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wire adc_up_pps_irq_mask_s;
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wire dac_up_pps_irq_mask_s;
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@ -535,23 +537,36 @@ module axi_ad9361 #(
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end
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endgenerate
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// GPS's 1PPS receiver
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ad_pps_receiver i_pps_receiver (
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.clk (clk),
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.rst (rst),
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.gps_pps (gps_pps),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_pps_rcounter (up_pps_rcounter_s),
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.up_irq_mask (up_irq_mask_s),
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.up_irq (gps_pps_irq));
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assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s;
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generate if (PPS_RECEIVER_ENABLE == 1) begin
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// GPS's PPS receiver
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ad_pps_receiver i_pps_receiver (
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.clk (clk),
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.rst (rst),
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.gps_pps (gps_pps),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_pps_rcounter (up_pps_rcounter_s),
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.up_pps_status (up_pps_status_s),
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.up_irq_mask (up_irq_mask_s),
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.up_irq (gps_pps_irq));
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assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s;
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end
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endgenerate
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generate if (PPS_RECEIVER_ENABLE == 0) begin
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assign up_pps_rcounter_s = 32'b0;
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assign up_pps_status_s = 1'b1;
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assign gps_pps_irq = 1'b0;
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end
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endgenerate
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// receive
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axi_ad9361_rx #(
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.ID (ID),
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.MODE_1R1T (MODE_1R1T),
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.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
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.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
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.INIT_DELAY (ADC_INIT_DELAY),
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.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
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.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
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@ -561,6 +576,7 @@ module axi_ad9361 #(
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.mmcm_rst (mmcm_rst),
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.adc_rst (rst),
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.adc_clk (clk),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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@ -589,7 +605,8 @@ module axi_ad9361 #(
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.adc_dunf (adc_dunf),
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.up_adc_gpio_in (up_adc_gpio_in),
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.up_adc_gpio_out (up_adc_gpio_out),
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.up_pps_rcounter(up_pps_rcounter_s),
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.up_pps_rcounter (up_pps_rcounter_s),
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.up_pps_status (up_pps_status_s),
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.up_pps_irq_mask (adc_up_pps_irq_mask_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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@ -614,6 +631,8 @@ module axi_ad9361 #(
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axi_ad9361_tx #(
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.ID (ID),
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.MODE_1R1T (MODE_1R1T),
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.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
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.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
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.INIT_DELAY (DAC_INIT_DELAY),
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.DDS_DISABLE (DAC_DDS_DISABLE_INT),
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.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
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@ -648,7 +667,8 @@ module axi_ad9361 #(
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.dac_data_q1 (dac_data_q1),
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.dac_dovf(dac_dovf),
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.dac_dunf(dac_dunf),
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.up_pps_rcounter(up_pps_rcounter_s),
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.up_pps_rcounter (up_pps_rcounter_s),
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.up_pps_status (up_pps_status_s),
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.up_pps_irq_mask (dac_up_pps_irq_mask_s),
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.up_dac_gpio_in (up_dac_gpio_in),
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.up_dac_gpio_out (up_dac_gpio_out),
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@ -9,8 +9,11 @@ set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && I
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set_false_path -to [get_cells -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]
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set_property ASYNC_REG TRUE \
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[get_cells -hier *_pps_m*]
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[get_cells -hier *_pps_m*] \
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[get_cells -hier *_pps_status_m*]
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set_false_path -to [get_cells -hier -filter {name =~ *_pps_m_reg[0] && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *pps_status_reg && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ *up_pps_status_m_reg && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *up_pps_rcounter_reg* && IS_SEQUENTIAL}]
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@ -42,6 +42,8 @@ module axi_ad9361_rx #(
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter PPS_RECEIVER_ENABLE = 0,
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parameter INIT_DELAY = 0,
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0,
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@ -97,6 +99,7 @@ module axi_ad9361_rx #(
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// 1PPS reporting counter and interrupt
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input [31:0] up_pps_rcounter,
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input up_pps_status,
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output up_pps_irq_mask,
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// processor interface
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@ -124,7 +127,9 @@ module axi_ad9361_rx #(
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// configuration settings
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localparam CONFIG = (MODE_1R1T * 16) +
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localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
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(CMOS_OR_LVDS_N * 128) +
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(MODE_1R1T * 16) +
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(USERPORTS_DISABLE * 8) +
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(DATAFORMAT_DISABLE * 4) +
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(DCFILTER_DISABLE * 2) +
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@ -349,6 +354,7 @@ module axi_ad9361_rx #(
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.adc_sync (),
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.up_adc_ce (),
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.up_pps_rcounter (up_pps_rcounter),
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.up_pps_status (up_pps_status),
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.up_pps_irq_mask (up_pps_irq_mask),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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@ -41,6 +41,8 @@ module axi_ad9361_tx #(
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter PPS_RECEIVER_ENABLE = 0,
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parameter INIT_DELAY = 0,
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parameter DDS_DISABLE = 0,
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parameter USERPORTS_DISABLE = 0,
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@ -95,6 +97,7 @@ module axi_ad9361_tx #(
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// 1PPS reporting counter and interrupt
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input [31:0] up_pps_rcounter,
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input up_pps_status,
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output up_pps_irq_mask,
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// processor interface
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@ -112,7 +115,9 @@ module axi_ad9361_tx #(
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// configuration settings
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localparam CONFIG = (DDS_DISABLE * 64) +
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localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
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(CMOS_OR_LVDS_N * 128) +
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(DDS_DISABLE * 64) +
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(DELAYCNTRL_DISABLE * 32) +
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(MODE_1R1T * 16) +
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(USERPORTS_DISABLE * 8) +
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@ -351,6 +356,7 @@ module axi_ad9361_tx #(
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.dac_clk_ratio (32'd1),
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.up_dac_ce (),
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.up_pps_rcounter (up_pps_rcounter),
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.up_pps_status (up_pps_status),
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.up_pps_irq_mask (up_pps_irq_mask),
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.up_drp_sel (),
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.up_drp_wr (),
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@ -42,6 +42,7 @@ module ad_pps_receiver (
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input up_clk,
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input up_rstn,
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output reg [31:0] up_pps_rcounter,
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output reg up_pps_status,
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input up_irq_mask,
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output reg up_irq);
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@ -52,9 +53,11 @@ module ad_pps_receiver (
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reg [ 2:0] gps_pps_m = 3'b0;
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reg [ 2:0] up_pps_m = 3'b0;
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reg up_pps_status_m = 1'b0;
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reg pps_toggle = 1'b0;
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reg [31:0] free_rcounter = 32'b0;
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reg [31:0] pps_rcounter = 32'b0;
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reg pps_status = 1'b0;
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wire pps_posedge_s;
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wire up_pps_posedge_s;
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@ -74,11 +77,16 @@ module ad_pps_receiver (
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if (rst == 1'b1) begin
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free_rcounter <= 32'b0;
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pps_rcounter <= 32'b0;
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pps_status <= 1'b1;
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end else if (pps_posedge_s == 1'b1) begin
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free_rcounter <= 32'b0;
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pps_rcounter <= free_rcounter;
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pps_status <= 1'b0;
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end else begin
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free_rcounter <= free_rcounter + 32'b1;
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if (free_rcounter[28] == 1'b1) begin
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pps_status <= 1'b1;
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end
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end
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end
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@ -96,8 +104,12 @@ module ad_pps_receiver (
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if (up_rstn == 1'b0) begin
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up_pps_m <= 3'b0;
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up_pps_rcounter <= 1'b0;
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up_pps_status_m <= 1'b1;
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up_pps_status <= 1'b1;
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end else begin
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up_pps_m <= {up_pps_m[1:0], pps_toggle};
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up_pps_status_m <= pps_status;
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up_pps_status <= up_pps_status_m;
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if ((up_pps_m[2] ^ up_pps_m[1]) == 1'b1) begin
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up_pps_rcounter <= pps_rcounter;
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end
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@ -67,6 +67,7 @@ module up_adc_common #(
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output adc_sref_sync,
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output adc_sync,
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input [31:0] up_pps_rcounter,
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input up_pps_status,
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output reg up_pps_irq_mask,
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// channel interface
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@ -375,6 +376,7 @@ module up_adc_common #(
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8'h2e: up_rdata_int <= up_adc_gpio_in;
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8'h2f: up_rdata_int <= up_adc_gpio_out_int;
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8'h30: up_rdata_int <= up_pps_rcounter;
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8'h31: up_rdata_int <= {31'b0, up_pps_status};
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default: up_rdata_int <= 0;
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endcase
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end else begin
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@ -68,6 +68,7 @@ module up_dac_common #(
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input [31:0] dac_clk_ratio,
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output up_dac_ce,
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input [31:0] up_pps_rcounter,
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input up_pps_status,
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output reg up_pps_irq_mask,
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// drp interface
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@ -378,6 +379,7 @@ module up_dac_common #(
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8'h2e: up_rdata_int <= up_dac_gpio_in;
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8'h2f: up_rdata_int <= up_dac_gpio_out_int;
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8'h30: up_rdata_int <= up_pps_rcounter;
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8'h31: up_rdata_int <= up_pps_status;
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default: up_rdata_int <= 0;
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endcase
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end else begin
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@ -11,6 +11,10 @@ set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
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# enable PPS receiver
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ad_ip_parameter axi_ad9361 CONFIG.PPS_RECEIVER_ENABLE 1
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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@ -11,6 +11,10 @@ set_property CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA0 1 [get_bd_cells sys_ps7]
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set_property CONFIG.PCW_USE_DMA1 1 [get_bd_cells sys_ps7]
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# enable PPS receiver
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ad_ip_parameter axi_ad9361 CONFIG.PPS_RECEIVER_ENABLE 1
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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Reference in New Issue