From 7c98a783c5d1d5bcd0cee15d5335025aa785a71c Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Tue, 23 Sep 2014 12:32:33 -0400
Subject: [PATCH] 2014.2 updates

---
 projects/common/zc706/zc706_system_plddr3.tcl | 6 +++---
 projects/fmcadc3/common/fmcadc3_spi.v         | 2 +-
 projects/fmcadc3/zc706/system_top.v           | 8 ++++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl
index 4639c4a89..addce5199 100644
--- a/projects/common/zc706/zc706_system_plddr3.tcl
+++ b/projects/common/zc706/zc706_system_plddr3.tcl
@@ -40,7 +40,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
   set_property -dict [list CONFIG.M_DATA_WIDTH {512}] $rfifo_ctl
   set_property -dict [list CONFIG.S_DATA_WIDTH {64}] $rfifo_ctl
 
-  set wfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 wfifo_mem]
+  set wfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 wfifo_mem]
   set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $wfifo_mem
   set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $wfifo_mem
   set_property -dict [list CONFIG.Input_Data_Width $m_width] $wfifo_mem
@@ -48,7 +48,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
   set_property -dict [list CONFIG.Output_Data_Width {512}] $wfifo_mem
   set_property -dict [list CONFIG.Overflow_Flag {true}] $wfifo_mem
 
-  set rfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 rfifo_mem]
+  set rfifo_mem [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:12.0 rfifo_mem]
   set_property -dict [list CONFIG.INTERFACE_TYPE {Native}] $rfifo_mem
   set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $rfifo_mem
   set_property -dict [list CONFIG.Input_Data_Width {512}] $rfifo_mem
@@ -66,7 +66,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
   set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_fifo2s
   set_property -dict [list CONFIG.DATA_WIDTH {512}] $axi_fifo2s
 
-  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl]
+  set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.1 axi_ddr_cntrl]
   set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
   file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
   set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v
index a038044cf..34366672c 100644
--- a/projects/fmcadc3/common/fmcadc3_spi.v
+++ b/projects/fmcadc3/common/fmcadc3_spi.v
@@ -37,7 +37,7 @@
 
 `timescale 1ns/100ps
 
-module daq2_spi (
+module fmcadc3_spi (
 
   ad9528_csn,
   ad9234_1_csn,
diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v
index 089932a70..1f173ebf9 100644
--- a/projects/fmcadc3/zc706/system_top.v
+++ b/projects/fmcadc3/zc706/system_top.v
@@ -109,10 +109,10 @@ module system_top (
   
   ad9528_rstn,
   ad9528_status,
-  ad9234_1_fda;
-  ad9234_1_fdb;
-  ad9234_2_fda;
-  ad9234_2_fdb;
+  ad9234_1_fda,
+  ad9234_1_fdb,
+  ad9234_2_fda,
+  ad9234_2_fdb,
  
   ad9528_csn,
   ada4961_1a_csn,