daq3: compilation fixes - latest changes
Rejeesh Kutty
parent
82b9ebe23d
commit
7c3ed75b79
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@ -63,11 +63,10 @@ if {$sys_zynq == 0} {
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set adc_dsync [create_bd_port -dir I adc_dsync]
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set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata]
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if {$sys_zynq == 1} {
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set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
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set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
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}
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set axi_ad9152_dma_intr [create_bd_port -dir O axi_ad9152_dma_intr]
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set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr]
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set axi_daq3_spi_intr [create_bd_port -dir O axi_daq3_spi_intr ]
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set axi_daq3_gpio_intr [create_bd_port -dir O axi_daq3_gpio_intr ]
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# dac peripherals
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@ -118,11 +117,6 @@ if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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if {$sys_zynq == 1} {
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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}
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if {$sys_zynq == 1} {
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set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect]
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@ -132,7 +126,8 @@ if {$sys_zynq == 1} {
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# dac/adc common gt/gpio
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set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq3_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq3_gt
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@ -174,7 +169,6 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 0} {
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set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
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set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
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}
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if {$sys_zynq == 1} {
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@ -194,31 +188,6 @@ if {$sys_zynq == 1} {
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set_property LEFT 42 [get_bd_ports GPIO_T]
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}
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# connections (pl ddr3)
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if {$sys_zynq == 1} {
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connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3]
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connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk]
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}
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# fmc dma clocks
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if {$sys_zynq == 1} {
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set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset]
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk]
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connect_bd_net -net sys_fmc_dma_async_reset \
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[get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \
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[get_bd_pins sys_ps7/FCLK_RESET2_N]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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}
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# connections (spi and gpio)
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if {$sys_zynq == 0} {
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@ -254,12 +223,6 @@ if {$sys_zynq == 0} {
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq3_gpio/gpio2_io_t]
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}
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if {$sys_zynq == 0} {
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delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2]
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delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3]
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}
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# connections (gt)
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connect_bd_net -net axi_daq3_gt_ref_clk_q [get_bd_pins axi_daq3_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
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@ -299,7 +262,7 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en]
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connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout]
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connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow]
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connect_bd_net -net axi_ad9152_dma_irq [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12]
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connect_bd_net -net axi_ad9152_dma_intr [get_bd_pins axi_ad9152_dma/irq] [get_bd_ports axi_ad9152_dma_intr]
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# connections (adc)
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@ -321,29 +284,25 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_daq3_gt_rx_ip_data [get_bd_pins axi_daq3_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
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connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins axi_daq3_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
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if {$sys_zynq == 1} {
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connect_bd_net -net axi_daq3_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq3_gt/rx_rst]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_fifo/dma_rstn] $sys_fmc_dma_resetn_source
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connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk]
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connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf]
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connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0]
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connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0]
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connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0]
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connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1]
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connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1]
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connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1]
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connect_bd_net -net axi_daq3_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq3_gt/rx_rst]
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connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk]
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connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf]
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connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_fifo/adc_wr]
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connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_fifo/adc_wdata]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk]
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connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
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connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk]
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connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/s_axis_valid]
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connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
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connect_bd_net -net axi_ad9680_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req]
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connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
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}
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connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
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connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/dma_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req]
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connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr]
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# dac/adc clocks
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@ -402,8 +361,8 @@ if {$sys_zynq == 0} {
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_spi/s_axi_aresetn]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gpio/s_axi_aresetn]
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connect_bd_net -net axi_daq3_spi_irq [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
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connect_bd_net -net axi_daq3_gpio_irq [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
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connect_bd_net -net axi_daq3_spi_intr [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_ports axi_daq3_spi_intr]
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connect_bd_net -net axi_daq3_gpio_intr [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_ports axi_daq3_gpio_intr]
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}
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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@ -440,71 +399,53 @@ if {$sys_zynq == 0} {
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if {$sys_zynq == 0} {
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connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
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connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source
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connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source
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connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
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} else {
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connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
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connect_bd_intf_net -intf_net axi_ad9152_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9152_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9152_dma/m_src_axi]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/M00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma_interconnect/S00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9152_dma/m_src_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9152_dma/m_src_axi_aresetn]
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connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
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connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
|
||||
}
|
||||
|
||||
# ila
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins axi_daq3_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins axi_daq3_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_daq3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_daq3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_daq3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_daq3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
|
||||
set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon
|
||||
|
||||
connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins axi_daq3_gt/tx_mon_data]
|
||||
connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins axi_daq3_gt/tx_mon_trigger]
|
||||
connect_bd_net -net axi_daq3_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK]
|
||||
connect_bd_net -net axi_daq3_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0]
|
||||
connect_bd_net -net axi_daq3_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1]
|
||||
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
|
||||
# address map
|
||||
|
||||
|
|
@ -524,9 +465,9 @@ if {$sys_zynq == 0} {
|
|||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9152_dma/m_src_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] $sys_addr_mem_seg SEG_axi_ddr_cntrl
|
||||
|
||||
} else {
|
||||
|
||||
|
|
@ -534,6 +475,5 @@ if {$sys_zynq == 0} {
|
|||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
|
||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue