From 7befef66624de8fc8348b497679ec3086cd4e6b9 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 13 Mar 2015 18:52:57 +0200 Subject: [PATCH] fmcomms2_zed: Update design to the new hdl framework --- projects/common/zed/zed_system_bd.tcl | 369 +++++++++++------------ projects/fmcomms2/zed/system_bd.tcl | 1 + projects/fmcomms2/zed/system_project.tcl | 4 +- projects/fmcomms2/zed/system_top.v | 207 ++++++------- 4 files changed, 284 insertions(+), 297 deletions(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index b1c251eac..0a3244fda 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -2,46 +2,80 @@ # create board design # interface ports -set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR] -set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO] -set IIC_FMC [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_FMC] +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc -set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I] -set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O] -set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T] +create_bd_port -dir O spi0_csn_2_o +create_bd_port -dir O spi0_csn_1_o +create_bd_port -dir O spi0_csn_0_o +create_bd_port -dir I spi0_csn_i +create_bd_port -dir I spi0_clk_i +create_bd_port -dir O spi0_clk_o +create_bd_port -dir I spi0_sdo_i +create_bd_port -dir O spi0_sdo_o +create_bd_port -dir I spi0_sdi_i + +create_bd_port -dir O spi1_csn_2_o +create_bd_port -dir O spi1_csn_1_o +create_bd_port -dir O spi1_csn_0_o +create_bd_port -dir I spi1_csn_i +create_bd_port -dir I spi1_clk_i +create_bd_port -dir O spi1_clk_o +create_bd_port -dir I spi1_sdo_i +create_bd_port -dir O spi1_sdo_o +create_bd_port -dir I spi1_sdi_i + +create_bd_port -dir I -from 63 -to 0 gpio_i +create_bd_port -dir O -from 63 -to 0 gpio_o +create_bd_port -dir O -from 63 -to 0 gpio_t # hdmi interface -set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] -set hdmi_hsync [create_bd_port -dir O hdmi_hsync] -set hdmi_vsync [create_bd_port -dir O hdmi_vsync] -set hdmi_data_e [create_bd_port -dir O hdmi_data_e] -set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data] +create_bd_port -dir O hdmi_out_clk +create_bd_port -dir O hdmi_hsync +create_bd_port -dir O hdmi_vsync +create_bd_port -dir O hdmi_data_e +create_bd_port -dir O -from 15 -to 0 hdmi_data # i2s -set i2s_mclk [create_bd_port -dir O -type clk i2s_mclk] -set i2s_bclk [create_bd_port -dir O i2s_bclk] -set i2s_lrclk [create_bd_port -dir O i2s_lrclk] -set i2s_sdata_out [create_bd_port -dir O i2s_sdata_out] -set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in] +create_bd_port -dir O -type clk i2s_mclk +create_bd_port -dir O i2s_bclk +create_bd_port -dir O i2s_lrclk +create_bd_port -dir O i2s_sdata_out +create_bd_port -dir I i2s_sdata_in # iic mux -set iic_mux_scl_I [create_bd_port -dir I -from 1 -to 0 iic_mux_scl_I] -set iic_mux_scl_O [create_bd_port -dir O -from 1 -to 0 iic_mux_scl_O] -set iic_mux_scl_T [create_bd_port -dir O iic_mux_scl_T] -set iic_mux_sda_I [create_bd_port -dir I -from 1 -to 0 iic_mux_sda_I] -set iic_mux_sda_O [create_bd_port -dir O -from 1 -to 0 iic_mux_sda_O] -set iic_mux_sda_T [create_bd_port -dir O iic_mux_sda_T ] +create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i +create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o +create_bd_port -dir O iic_mux_scl_t +create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i +create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o +create_bd_port -dir O iic_mux_sda_t -set otg_vbusoc [create_bd_port -dir I otg_vbusoc] +create_bd_port -dir I otg_vbusoc # spdif audio -set spdif [create_bd_port -dir O spdif] +create_bd_port -dir O spdif -set iic_fmc_intr [create_bd_port -dir O iic_fmc_intr] +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 # instance: sys_ps7 @@ -56,11 +90,15 @@ set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main] set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main @@ -71,10 +109,6 @@ set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer: set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc -set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] -set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect -set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect - set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen @@ -92,9 +126,6 @@ set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma -set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect] -set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect - # audio peripherals set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] @@ -117,191 +148,147 @@ set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic # system reset/clock definitions -set sys_100m_clk_source [get_bd_pins sys_ps7/FCLK_CLK0] -set sys_200m_clk_source [get_bd_pins sys_ps7/FCLK_CLK1] - -connect_bd_net -net sys_100m_clk $sys_100m_clk_source -connect_bd_net -net sys_200m_clk $sys_200m_clk_source - -connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk] -connect_bd_net -net sys_aux_reset [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET0_N] - -set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] -set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn] -connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source -connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N # interface connections -connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR] -connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I] -connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O] -connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T] -connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO] +ad_connect ddr sys_ps7/DDR +ad_connect gpio_i sys_ps7/GPIO_I +ad_connect gpio_o sys_ps7/GPIO_O +ad_connect gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO +ad_connect iic_fmc axi_iic_fmc/iic +ad_connect sys_200m_clk axi_hdmi_clkgen/clk -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source +ad_connect axi_iic_main/scl_i sys_i2c_mixer/upstream_scl_o +ad_connect axi_iic_main/scl_o sys_i2c_mixer/upstream_scl_i +ad_connect axi_iic_main/scl_t sys_i2c_mixer/upstream_scl_t +ad_connect axi_iic_main/sda_i sys_i2c_mixer/upstream_sda_o +ad_connect axi_iic_main/sda_o sys_i2c_mixer/upstream_sda_i +ad_connect axi_iic_main/sda_t sys_i2c_mixer/upstream_sda_t -connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source +ad_connect iic_mux_scl_i sys_i2c_mixer/downstream_scl_i +ad_connect iic_mux_scl_o sys_i2c_mixer/downstream_scl_o +ad_connect iic_mux_scl_t sys_i2c_mixer/downstream_scl_t +ad_connect iic_mux_sda_i sys_i2c_mixer/downstream_sda_i +ad_connect iic_mux_sda_o sys_i2c_mixer/downstream_sda_o +ad_connect iic_mux_sda_t sys_i2c_mixer/downstream_sda_t -connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] +ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT +ad_connect otg_vbusoc sys_logic_inv/Op1 -connect_bd_net -net axi_iic_main_scl_i [get_bd_pins axi_iic_main/scl_i] [get_bd_pins sys_i2c_mixer/upstream_scl_O] -connect_bd_net -net axi_iic_main_scl_o [get_bd_pins axi_iic_main/scl_o] [get_bd_pins sys_i2c_mixer/upstream_scl_I] -connect_bd_net -net axi_iic_main_scl_t [get_bd_pins axi_iic_main/scl_t] [get_bd_pins sys_i2c_mixer/upstream_scl_T] -connect_bd_net -net axi_iic_main_sda_i [get_bd_pins axi_iic_main/sda_i] [get_bd_pins sys_i2c_mixer/upstream_sda_O] -connect_bd_net -net axi_iic_main_sda_o [get_bd_pins axi_iic_main/sda_o] [get_bd_pins sys_i2c_mixer/upstream_sda_I] -connect_bd_net -net axi_iic_main_sda_t [get_bd_pins axi_iic_main/sda_t] [get_bd_pins sys_i2c_mixer/upstream_sda_T] +# spi connections -connect_bd_net -net sys_i2c_mixer_downstream_scl_i [get_bd_ports iic_mux_scl_I] [get_bd_pins sys_i2c_mixer/downstream_scl_I] -connect_bd_net -net sys_i2c_mixer_downstream_scl_o [get_bd_ports iic_mux_scl_O] [get_bd_pins sys_i2c_mixer/downstream_scl_O] -connect_bd_net -net sys_i2c_mixer_downstream_scl_t [get_bd_ports iic_mux_scl_T] [get_bd_pins sys_i2c_mixer/downstream_scl_T] -connect_bd_net -net sys_i2c_mixer_downstream_sda_i [get_bd_ports iic_mux_sda_I] [get_bd_pins sys_i2c_mixer/downstream_sda_I] -connect_bd_net -net sys_i2c_mixer_downstream_sda_o [get_bd_ports iic_mux_sda_O] [get_bd_pins sys_i2c_mixer/downstream_sda_O] -connect_bd_net -net sys_i2c_mixer_downstream_sda_t [get_bd_ports iic_mux_sda_T] [get_bd_pins sys_i2c_mixer/downstream_sda_T] +ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O +ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O +ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O +ad_connect spi0_csn_i sys_ps7/SPI0_SS_I +ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I +ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O +ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I +ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O +ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I -connect_bd_net -net sys_logic_inv_o [get_bd_pins sys_logic_inv/Res] [get_bd_pins sys_ps7/USB0_VBUS_PWRFAULT] -connect_bd_net -net sys_logic_inv_i [get_bd_pins sys_logic_inv/Op1] [get_bd_ports otg_vbusoc] +ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O +ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O +ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O +ad_connect spi1_csn_i sys_ps7/SPI1_SS_I +ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I +ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O +ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I +ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O +ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I # hdmi -connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk] +ad_connect sys_cpu_clk axi_hdmi_clkgen/drp_clk +ad_connect sys_cpu_clk axi_hdmi_core/m_axis_mm2s_clk +ad_connect sys_cpu_clk axi_hdmi_dma/s_axi_lite_aclk +ad_connect sys_cpu_clk axi_hdmi_dma/m_axi_mm2s_aclk +ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk -connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE] +ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0 +ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk +ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync +ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync +ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e +ad_connect axi_hdmi_core/hdmi_16_data hdmi_data +ad_connect axi_hdmi_core/m_axis_mm2s_tvalid axi_hdmi_dma/m_axis_mm2s_tvalid +ad_connect axi_hdmi_core/m_axis_mm2s_tdata axi_hdmi_dma/m_axis_mm2s_tdata +ad_connect axi_hdmi_core/m_axis_mm2s_tkeep axi_hdmi_dma/m_axis_mm2s_tkeep +ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast +ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready +ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync -connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] -connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0] - -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK] - -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn] - -connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0] -connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk] -connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync] -connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync] -connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e] -connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data] -connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] -connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] -connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] -connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] -connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] -connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] -connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] +ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret # spdif audio -connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] +ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN] -connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ] -connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK] - -connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] -connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source -connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] -connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] +ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ +ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK +ad_connect sys_100m_resetn axi_spdif_tx_core/DMA_REQ_RSTN +ad_connect sys_200m_clk sys_audio_clkgen/clk_in1 +ad_connect sys_cpu_resetn sys_audio_clkgen/resetn +ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk +ad_connect spdif axi_spdif_tx_core/spdif_tx_o # i2s audio -connect_bd_intf_net -intf_net axi_cpu_interconnect_m05_axi [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_i2s_adi/s_axi] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/S_AXI_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_RX_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_TX_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA1_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA2_ACLK] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/S_AXI_ARESETN] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_RX_RSTN] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_TX_RSTN] +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK +ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK +ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK -connect_bd_net -net sys_audio_clkgen_clk [get_bd_ports i2s_mclk] -connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins axi_i2s_adi/DATA_CLK_I] +ad_connect sys_audio_clkgen/clk_out1 i2s_mclk +ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I -connect_bd_net -net i2s_bclk_s [get_bd_ports i2s_bclk] [get_bd_pins axi_i2s_adi/BCLK_O] -connect_bd_net -net i2s_lrclk_s [get_bd_ports i2s_lrclk] [get_bd_pins axi_i2s_adi/LRCLK_O] -connect_bd_net -net i2s_sdata_out_s [get_bd_ports i2s_sdata_out] [get_bd_pins axi_i2s_adi/SDATA_O] -connect_bd_net -net i2s_sdata_in_s [get_bd_ports i2s_sdata_in] [get_bd_pins axi_i2s_adi/SDATA_I] +ad_connect i2s_bclk axi_i2s_adi/BCLK_O +ad_connect i2s_lrclk axi_i2s_adi/LRCLK_O +ad_connect i2s_sdata_out axi_i2s_adi/SDATA_O +ad_connect i2s_sdata_in axi_i2s_adi/SDATA_I -connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_tx [get_bd_intf_pins sys_ps7/DMA1_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_TX] -connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA1_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_TX] -connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_rx [get_bd_intf_pins sys_ps7/DMA2_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_RX] -connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_rx [get_bd_intf_pins sys_ps7/DMA2_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_RX] - -# iic (fmc) - -connect_bd_intf_net -intf_net axi_cpu_interconnect_m06_axi [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_iic_fmc/s_axi] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_fmc/s_axi_aclk] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_fmc/s_axi_aresetn] - -connect_bd_intf_net -intf_net axi_iic_fmc_iic [get_bd_intf_ports IIC_FMC] [get_bd_intf_pins axi_iic_fmc/iic] - -connect_bd_net -net axi_iic_fmc_intr [get_bd_pins axi_iic_fmc/iic2intc_irpt] [get_bd_ports iic_fmc_intr] +ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX +ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX +ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX +ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX # interrupts -connect_bd_net [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P] -connect_bd_net [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt] +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut +ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 axi_iic_fmc/iic2intc_irpt +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 -for {set intc_index 0} {$intc_index < 14} {incr intc_index} { - set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] -} +# interconnects and address mapping -# address map - -set sys_zynq 1 -set sys_mem_size 0x20000000 -set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data] - -create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main -create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen -create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma -create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core -create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core -create_bd_addr_seg -range 0x00010000 -offset 0x77600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0] SEG_data_i2s_adi -create_bd_addr_seg -range 0x00010000 -offset 0x41620000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_fmc/s_axi/Reg] SEG_data_iic_fmc - -create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen +ad_cpu_interconnect 0x43000000 axi_hdmi_dma +ad_cpu_interconnect 0x70e00000 axi_hdmi_core +ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core +ad_cpu_interconnect 0x77600000 axi_i2s_adi +ad_cpu_interconnect 0x41620000 axi_iic_fmc +ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0 +ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S diff --git a/projects/fmcomms2/zed/system_bd.tcl b/projects/fmcomms2/zed/system_bd.tcl index 6011d84db..37eb52875 100644 --- a/projects/fmcomms2/zed/system_bd.tcl +++ b/projects/fmcomms2/zed/system_bd.tcl @@ -1,4 +1,5 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl source ../common/fmcomms2_bd.tcl diff --git a/projects/fmcomms2/zed/system_project.tcl b/projects/fmcomms2/zed/system_project.tcl index 4a758ce65..330fca68a 100644 --- a/projects/fmcomms2/zed/system_project.tcl +++ b/projects/fmcomms2/zed/system_project.tcl @@ -1,8 +1,7 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcomms2_zed adi_project_files fmcomms2_zed [list \ @@ -13,4 +12,3 @@ adi_project_files fmcomms2_zed [list \ adi_project_run fmcomms2_zed - diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 1f08eb0bb..20ba5da22 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -41,28 +41,28 @@ module system_top ( - DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, gpio_bd, @@ -118,28 +118,28 @@ module system_top ( spi_udc_sclk, spi_udc_data); - inout [14:0] DDR_addr; - inout [ 2:0] DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [ 3:0] DDR_dm; - inout [31:0] DDR_dq; - inout [ 3:0] DDR_dqs_n; - inout [ 3:0] DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0] FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; inout [31:0] gpio_bd; @@ -197,9 +197,9 @@ module system_top ( // internal signals - wire [48:0] gpio_i; - wire [48:0] gpio_o; - wire [48:0] gpio_t; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; wire [ 1:0] iic_mux_scl_i_s; wire [ 1:0] iic_mux_scl_o_s; wire iic_mux_scl_t_s; @@ -236,30 +236,30 @@ module system_top ( .dio(iic_mux_sda)); system_wrapper i_system_wrapper ( - .DDR_addr (DDR_addr), - .DDR_ba (DDR_ba), - .DDR_cas_n (DDR_cas_n), - .DDR_ck_n (DDR_ck_n), - .DDR_ck_p (DDR_ck_p), - .DDR_cke (DDR_cke), - .DDR_cs_n (DDR_cs_n), - .DDR_dm (DDR_dm), - .DDR_dq (DDR_dq), - .DDR_dqs_n (DDR_dqs_n), - .DDR_dqs_p (DDR_dqs_p), - .DDR_odt (DDR_odt), - .DDR_ras_n (DDR_ras_n), - .DDR_reset_n (DDR_reset_n), - .DDR_we_n (DDR_we_n), - .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), - .FIXED_IO_mio (FIXED_IO_mio), - .FIXED_IO_ps_clk (FIXED_IO_ps_clk), - .FIXED_IO_ps_porb (FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), - .GPIO_I (gpio_i), - .GPIO_O (gpio_o), - .GPIO_T (gpio_t), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -272,29 +272,27 @@ module system_top ( .i2s_sdata_out (i2s_sdata_out), .iic_fmc_scl_io (iic_scl), .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_I (iic_mux_scl_i_s), - .iic_mux_scl_O (iic_mux_scl_o_s), - .iic_mux_scl_T (iic_mux_scl_t_s), - .iic_mux_sda_I (iic_mux_sda_i_s), - .iic_mux_sda_O (iic_mux_sda_o_s), - .iic_mux_sda_T (iic_mux_sda_t_s), - .ps_intr_0 (ps_intrs[0]), - .ps_intr_1 (ps_intrs[1]), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .ps_intr_00 (ps_intrs[0]), + .ps_intr_01 (ps_intrs[1]), + .ps_intr_02 (ps_intrs[2]), + .ps_intr_03 (ps_intrs[3]), + .ps_intr_04 (ps_intrs[4]), + .ps_intr_05 (ps_intrs[5]), + .ps_intr_06 (ps_intrs[6]), + .ps_intr_07 (ps_intrs[7]), + .ps_intr_08 (ps_intrs[8]), + .ps_intr_09 (ps_intrs[9]), .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), .ps_intr_13 (ps_intrs[13]), - .ps_intr_2 (ps_intrs[2]), - .ps_intr_3 (ps_intrs[3]), - .ps_intr_4 (ps_intrs[4]), - .ps_intr_5 (ps_intrs[5]), - .ps_intr_6 (ps_intrs[6]), - .ps_intr_7 (ps_intrs[7]), - .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), .ad9361_dac_dma_irq (ps_intrs[12]), .ad9361_adc_dma_irq (ps_intrs[13]), - .iic_fmc_intr(ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), @@ -303,27 +301,30 @@ module system_top ( .rx_frame_in_n (rx_frame_in_n), .rx_frame_in_p (rx_frame_in_p), .spdif (spdif), - .spi_csn_i (1'b1), - .spi_csn_o (spi_csn), - .spi_miso_i (spi_miso), - .spi_mosi_i (1'b0), - .spi_mosi_o (spi_mosi), - .spi_sclk_i (1'b0), - .spi_sclk_o (spi_clk), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (spi_udc_sclk), + .spi1_csn_0_o (spi_udc_csn_tx), + .spi1_csn_1_o (spi_udc_csn_rx), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (spi_udc_data), + .spi1_sdo_o (spi_udc_data), .tx_clk_out_n (tx_clk_out_n), .tx_clk_out_p (tx_clk_out_p), .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .spi_udc_clk_i (1'b0), - .spi_udc_clk_o (spi_udc_sclk), - .spi_udc_csn_i (1'b1), - .spi_udc_csn_tx_o (spi_udc_csn_tx), - .spi_udc_csn_rx_o (spi_udc_csn_rx), - .spi_udc_mosi_i (spi_udc_data), - .spi_udc_mosi_o (spi_udc_data), - .spi_udc_miso_i (1'b0)); + .tx_frame_out_p (tx_frame_out_p)); endmodule