adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
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6d504d14cf
commit
7be66b63c1
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@ -349,7 +349,11 @@ ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_
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ad_connect sys_cpu_resetn util_adrv9009_som_xcvr/up_rstn
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ad_connect sys_cpu_resetn util_adrv9009_som_xcvr/up_rstn
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ad_connect sys_cpu_clk util_adrv9009_som_xcvr/up_clk
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ad_connect sys_cpu_clk util_adrv9009_som_xcvr/up_clk
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if {$TX_NUM_OF_LANES == 16} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16} core_clk_a
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} else {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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}
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if {$RX_NUM_OF_LANES == 8} {
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if {$RX_NUM_OF_LANES == 8} {
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5 8 9 12 13} core_clk_b
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {0 1 4 5 8 9 12 13} core_clk_b
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