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daq2: zc706: Increase DAC FIFO size 

Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-28 11:29:12 +02:00
parent f6eea23f5e
commit 7a53b99b8b
1 changed files with 1 additions and 1 deletions
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projects/daq2/zc706/system_bd.tcl
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@ -5,7 +5,7 @@ set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128