From 7a53b99b8b205a0e16c1ab2116d17c662d526637 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 28 Apr 2017 11:29:12 +0200 Subject: [PATCH] daq2: zc706: Increase DAC FIFO size Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is quite a limiting size for practical applications. Increase the size to 1MB to allow loading larger waveforms. In this configuration the DAC FIFO will use half of the available BRAM cells in the FPGA. This still leaves quite a few BRAMs available for user application logic added to the design. If a user design should run out of BRAMs nevertheless they can reduce the FIFO size, if not required by the application, to free up some cells. Signed-off-by: Lars-Peter Clausen --- projects/daq2/zc706/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index 1efd3a4df..955785133 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -5,7 +5,7 @@ set adc_data_width 128 set adc_dma_data_width 64 set dac_fifo_name axi_ad9144_fifo -set dac_fifo_address_width 10 +set dac_fifo_address_width 16 set dac_data_width 128 set dac_dma_data_width 128