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adi_ip_alt.tcl: ad_ip_intf_s_axi: Allow to specify AXI interface address width 

The address width of the AXI interface depends on the size of the register
and can differ from peripheral to peripheral. Add a parameter to the
function that allows to specify the address width, this allows to use the
function for more peripherals.

Keep the current value of 16 bits as the default if the parameter is not
specified.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-19 19:16:15 +02:00
parent e1e0406a49
commit 7a04b4723b
1 changed files with 3 additions and 3 deletions
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6
library/scripts/adi_ip_alt.tcl
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@ -171,7 +171,7 @@ proc ad_ip_files {pname pfiles {pfunction ""}} {
###################################################################################################
###################################################################################################
proc ad_ip_intf_s_axi {aclk arstn} {
proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} {
add_interface s_axi_clock clock end
add_interface_port s_axi_clock ${aclk} clk Input 1
@ -184,7 +184,7 @@ proc ad_ip_intf_s_axi {aclk arstn} {
set_interface_property s_axi associatedClock s_axi_clock
set_interface_property s_axi associatedReset s_axi_reset
add_interface_port s_axi s_axi_awvalid awvalid Input 1
add_interface_port s_axi s_axi_awaddr awaddr Input 16
add_interface_port s_axi s_axi_awaddr awaddr Input $addr_width
add_interface_port s_axi s_axi_awprot awprot Input 3
add_interface_port s_axi s_axi_awready awready Output 1
add_interface_port s_axi s_axi_wvalid wvalid Input 1
@ -195,7 +195,7 @@ proc ad_ip_intf_s_axi {aclk arstn} {
add_interface_port s_axi s_axi_bresp bresp Output 2
add_interface_port s_axi s_axi_bready bready Input 1
add_interface_port s_axi s_axi_arvalid arvalid Input 1
add_interface_port s_axi s_axi_araddr araddr Input 16
add_interface_port s_axi s_axi_araddr araddr Input $addr_width
add_interface_port s_axi s_axi_arprot arprot Input 3
add_interface_port s_axi s_axi_arready arready Output 1
add_interface_port s_axi s_axi_rvalid rvalid Output 1