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fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0

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Adrian Costina 2015-07-24 16:43:33 +03:00
parent 623c3dc333
commit 797d679c72
2 changed files with 130 additions and 84 deletions
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188
projects/fmcomms2/c5soc/system_bd.qsys
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File diff suppressed because one or more lines are too long

26
projects/fmcomms2/c5soc/system_top.v
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@ -287,8 +287,6 @@ module system_top (
wire dac_dunf;
wire dac_rd_en;
wire dac_fifo_valid;
wire [111:0] dev_dbg_data;
wire [ 61:0] dev_l_dbg_data;
wire vga_pixel_clock;
wire vid_v_sync;
wire vid_h_sync;
@ -449,18 +447,18 @@ module system_top (
.axi_ad9361_dma_if_dac_data_q1 (dac_data_q1),
.axi_ad9361_dma_if_dac_dovf (),
.axi_ad9361_dma_if_dac_dunf (dac_dunf),
.axi_ad9361_debug_if_dev_dbg_data (dev_dbg_data),
.axi_ad9361_debug_if_dev_l_dbg_data (dev_l_dbg_data),
.axi_dmac_dac_fifo_rd_clock_clk (clk),
.axi_dmac_dac_fifo_rd_if_rden (dac_rd_en),
.axi_dmac_dac_fifo_rd_if_valid (dac_fifo_valid),
.axi_dmac_dac_fifo_rd_if_data (dac_ddata),
.axi_dmac_dac_fifo_rd_if_unf (dac_dunf),
.axi_dmac_adc_fifo_wr_clock_clk (clk),
.axi_dmac_adc_fifo_wr_if_ovf (adc_dovf),
.axi_dmac_adc_fifo_wr_if_wren (adc_dwr),
.axi_dmac_adc_fifo_wr_if_data (adc_ddata),
.axi_dmac_adc_fifo_wr_if_sync (adc_dsync),
.axi_dmac_dac_if_fifo_rd_clk_clk (clk),
.axi_dmac_dac_if_fifo_rd_en_dac_valid (dac_rd_en),
.axi_dmac_dac_if_fifo_rd_valid_dma_valid (dac_fifo_valid),
.axi_dmac_dac_if_fifo_rd_dout_dac_data (dac_ddata),
.axi_dmac_dac_if_fifo_rd_underflow_dac_dunf (dac_dunf),
.axi_dmac_dac_if_fifo_rd_xfer_req_dma_xfer_req (),
.axi_dmac_adc_if_fifo_wr_clk_clk (clk),
.axi_dmac_adc_if_fifo_wr_overflow_adc_dovf (adc_dovf),
.axi_dmac_adc_if_fifo_wr_en_adc_valid (adc_dwr),
.axi_dmac_adc_if_fifo_wr_din_adc_data (adc_ddata),
.axi_dmac_adc_if_fifo_wr_sync_adc_sync (adc_dsync),
.axi_dmac_adc_if_fifo_wr_xfer_req_dma_xfer_req (),
.spi_ad9361_external_MISO (spi_miso),
.spi_ad9361_external_MOSI (spi_mosi),
.spi_ad9361_external_SCLK (spi_clk),