From 78999e154e166bee19ff5e3e7ad0d9e3d2360170 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 15 Mar 2021 08:52:30 +0000 Subject: [PATCH] adrv9009zu11eg: Integrate data_offload --- .../adrv2crr_fmc/system_project.tcl | 3 + .../adrv9009zu11eg/adrv2crr_fmc/system_top.v | 107 ++++++--- .../common/adrv9009zu11eg_bd.tcl | 163 +++++++++----- .../common/adrv9009zu11eg_constr.xdc | 208 ++++++++++++------ 4 files changed, 321 insertions(+), 160 deletions(-) diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl b/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl index 9350c1383..04fac5a60 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl @@ -22,4 +22,7 @@ adi_project_files adrv9009zu11eg [list \ "../common/adrv2crr_fmc_constr.xdc" \ "$ad_hdl_dir/library/common/ad_iobuf.v" ] +## To improve timing in DDR4 MIG +set_property strategy Performance_ExploreWithRemap [get_runs impl_1] + adi_project_run adrv9009zu11eg diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v index f77c7100a..97ccc629c 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v @@ -194,25 +194,46 @@ module system_top ( output spi_csn_adrv9009_b, output spi_csn_hmc7044, - input ddr4_ref_1_clk_n, - input ddr4_ref_1_clk_p, + input ddr4_ref_clk_tx_offload_n, + input ddr4_ref_clk_tx_offload_p, + + output ddr4_if_tx_offload_act_n, + output [16:0] ddr4_if_tx_offload_adr, + output [1:0] ddr4_if_tx_offload_ba, + output [0:0] ddr4_if_tx_offload_bg, + output [0:0] ddr4_if_tx_offload_ck_c, + output [0:0] ddr4_if_tx_offload_ck_t, + output [0:0] ddr4_if_tx_offload_cke, + output [0:0] ddr4_if_tx_offload_cs_n, + inout [3:0] ddr4_if_tx_offload_dm_n, + inout [31:0] ddr4_if_tx_offload_dq, + inout [3:0] ddr4_if_tx_offload_dqs_c, + inout [3:0] ddr4_if_tx_offload_dqs_t, + output [0:0] ddr4_if_tx_offload_odt, + output ddr4_if_tx_offload_reset_n, + output ddr4_if_tx_offload_par, + input ddr4_if_tx_offload_alert_n, + + input ddr4_ref_clk_rx_offload_n, + input ddr4_ref_clk_rx_offload_p, + + output ddr4_if_rx_offload_act_n, + output [16:0] ddr4_if_rx_offload_adr, + output [1:0] ddr4_if_rx_offload_ba, + output [0:0] ddr4_if_rx_offload_bg, + output [0:0] ddr4_if_rx_offload_ck_c, + output [0:0] ddr4_if_rx_offload_ck_t, + output [0:0] ddr4_if_rx_offload_cke, + output [0:0] ddr4_if_rx_offload_cs_n, + inout [3:0] ddr4_if_rx_offload_dm_n, + inout [31:0] ddr4_if_rx_offload_dq, + inout [3:0] ddr4_if_rx_offload_dqs_c, + inout [3:0] ddr4_if_rx_offload_dqs_t, + output [0:0] ddr4_if_rx_offload_odt, + output ddr4_if_rx_offload_reset_n, + output ddr4_if_rx_offload_par, + input ddr4_if_rx_offload_alert_n, - output ddr4_rtl_1_act_n, - output [16:0] ddr4_rtl_1_adr, - output [1:0] ddr4_rtl_1_ba, - output [0:0] ddr4_rtl_1_bg, - output [0:0] ddr4_rtl_1_ck_c, - output [0:0] ddr4_rtl_1_ck_t, - output [0:0] ddr4_rtl_1_cke, - output [0:0] ddr4_rtl_1_cs_n, - inout [3:0] ddr4_rtl_1_dm_n, - inout [31:0] ddr4_rtl_1_dq, - inout [3:0] ddr4_rtl_1_dqs_c, - inout [3:0] ddr4_rtl_1_dqs_t, - output [0:0] ddr4_rtl_1_odt, - output ddr4_rtl_1_reset_n, - output ddr4_rtl_1_par, - input ddr4_rtl_1_alert_n, output spi_clk, inout spi_sdio, input spi_miso @@ -452,24 +473,38 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - - .ddr4_rtl_1_act_n(ddr4_rtl_1_act_n), - .ddr4_rtl_1_adr(ddr4_rtl_1_adr), - .ddr4_rtl_1_ba(ddr4_rtl_1_ba), - .ddr4_rtl_1_bg(ddr4_rtl_1_bg), - .ddr4_rtl_1_ck_c(ddr4_rtl_1_ck_c), - .ddr4_rtl_1_ck_t(ddr4_rtl_1_ck_t), - .ddr4_rtl_1_cke(ddr4_rtl_1_cke), - .ddr4_rtl_1_cs_n(ddr4_rtl_1_cs_n), - .ddr4_rtl_1_dm_n(ddr4_rtl_1_dm_n), - .ddr4_rtl_1_dq(ddr4_rtl_1_dq), - .ddr4_rtl_1_dqs_c(ddr4_rtl_1_dqs_c), - .ddr4_rtl_1_dqs_t(ddr4_rtl_1_dqs_t), - .ddr4_rtl_1_odt(ddr4_rtl_1_odt), - .ddr4_rtl_1_reset_n(ddr4_rtl_1_reset_n), - .sys_reset(1'b0), - .ddr4_ref_1_clk_n(ddr4_ref_1_clk_n), - .ddr4_ref_1_clk_p(ddr4_ref_1_clk_p), + .ddr4_if_tx_offload_act_n(ddr4_if_tx_offload_act_n), + .ddr4_if_tx_offload_adr(ddr4_if_tx_offload_adr), + .ddr4_if_tx_offload_ba(ddr4_if_tx_offload_ba), + .ddr4_if_tx_offload_bg(ddr4_if_tx_offload_bg), + .ddr4_if_tx_offload_ck_c(ddr4_if_tx_offload_ck_c), + .ddr4_if_tx_offload_ck_t(ddr4_if_tx_offload_ck_t), + .ddr4_if_tx_offload_cke(ddr4_if_tx_offload_cke), + .ddr4_if_tx_offload_cs_n(ddr4_if_tx_offload_cs_n), + .ddr4_if_tx_offload_dm_n(ddr4_if_tx_offload_dm_n), + .ddr4_if_tx_offload_dq(ddr4_if_tx_offload_dq), + .ddr4_if_tx_offload_dqs_c(ddr4_if_tx_offload_dqs_c), + .ddr4_if_tx_offload_dqs_t(ddr4_if_tx_offload_dqs_t), + .ddr4_if_tx_offload_odt(ddr4_if_tx_offload_odt), + .ddr4_if_tx_offload_reset_n(ddr4_if_tx_offload_reset_n), + .ddr4_ref_clk_tx_offload_clk_n(ddr4_ref_clk_tx_offload_n), + .ddr4_ref_clk_tx_offload_clk_p(ddr4_ref_clk_tx_offload_p), + .ddr4_if_rx_offload_act_n(ddr4_if_rx_offload_act_n), + .ddr4_if_rx_offload_adr(ddr4_if_rx_offload_adr), + .ddr4_if_rx_offload_ba(ddr4_if_rx_offload_ba), + .ddr4_if_rx_offload_bg(ddr4_if_rx_offload_bg), + .ddr4_if_rx_offload_ck_c(ddr4_if_rx_offload_ck_c), + .ddr4_if_rx_offload_ck_t(ddr4_if_rx_offload_ck_t), + .ddr4_if_rx_offload_cke(ddr4_if_rx_offload_cke), + .ddr4_if_rx_offload_cs_n(ddr4_if_rx_offload_cs_n), + .ddr4_if_rx_offload_dm_n(ddr4_if_rx_offload_dm_n), + .ddr4_if_rx_offload_dq(ddr4_if_rx_offload_dq), + .ddr4_if_rx_offload_dqs_c(ddr4_if_rx_offload_dqs_c), + .ddr4_if_rx_offload_dqs_t(ddr4_if_rx_offload_dqs_t), + .ddr4_if_rx_offload_odt(ddr4_if_rx_offload_odt), + .ddr4_if_rx_offload_reset_n(ddr4_if_rx_offload_reset_n), + .ddr4_ref_clk_rx_offload_clk_n(ddr4_ref_clk_rx_offload_n), + .ddr4_ref_clk_rx_offload_clk_p(ddr4_ref_clk_rx_offload_p), .core_clk_a(core_clk_a), .core_clk_b(core_clk_b), .ref_clk_a(ref_clk_a), diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl index 8b2234834..5139094fb 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl @@ -1,3 +1,6 @@ +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl + # default ports create_bd_port -dir O -from 2 -to 0 spi0_csn @@ -9,7 +12,7 @@ create_bd_port -dir I -from 94 -to 0 gpio_i create_bd_port -dir O -from 94 -to 0 gpio_o create_bd_port -dir O -from 94 -to 0 gpio_t -create_bd_port -dir I sys_reset +#create_bd_port -dir I sys_reset create_bd_port -dir I ref_clk_a create_bd_port -dir I ref_clk_b @@ -183,44 +186,83 @@ set OBS_SAMPLE_WIDTH 16 ; # N/NP set OBS_SAMPLES_PER_CHANNEL [expr ($OBS_NUM_OF_LANES * 32) / ($OBS_NUM_OF_CONVERTERS * $OBS_SAMPLE_WIDTH)] ; # L * 32 / (M * N) -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_rtl_1 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_ref_1 +# PL side DDR4 controller with TX data offload instance - 8 GByte -ad_ip_instance ip:ddr4 ddr4_1 -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_DataWidth {32} -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiDataWidth {256} -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiAddressWidth {31} -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_InputClockPeriod {3334} -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} -ad_ip_parameter ddr4_1 CONFIG.C0.BANK_GROUP_WIDTH {1} -ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_CasLatency {18} +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_if_tx_offload +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_ref_clk_tx_offload -ad_connect ddr4_rtl_1 ddr4_1/C0_DDR4 +ad_ip_instance ip:ddr4 ddr4_tx_offload +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_DataWidth {32} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_AxiDataWidth {256} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_AxiAddressWidth {31} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_InputClockPeriod {3334} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.BANK_GROUP_WIDTH {1} +ad_ip_parameter ddr4_tx_offload CONFIG.C0.DDR4_CasLatency {18} -set_property -dict [list CONFIG.FREQ_HZ {300000000}] [get_bd_intf_ports ddr4_ref_1] -ad_connect ddr4_ref_1 ddr4_1/C0_SYS_CLK +ad_connect ddr4_if_tx_offload ddr4_tx_offload/C0_DDR4 -set dac_fifo_name axi_tx_fifo -set dac_data_width [expr 32*$TX_NUM_OF_LANES] -set dac_dma_data_width [expr 32*$TX_NUM_OF_LANES] -set dac_fifo_address_width 31 +set_property -dict [list CONFIG.FREQ_HZ {300000000}] [get_bd_intf_ports ddr4_ref_clk_tx_offload] +ad_connect ddr4_ref_clk_tx_offload ddr4_tx_offload/C0_SYS_CLK -ad_ip_instance axi_dacfifo $dac_fifo_name -ad_ip_parameter $dac_fifo_name CONFIG.DAC_DATA_WIDTH $dac_data_width -ad_ip_parameter $dac_fifo_name CONFIG.DMA_DATA_WIDTH $dac_dma_data_width -ad_ip_parameter $dac_fifo_name CONFIG.AXI_DATA_WIDTH 256 -ad_ip_parameter $dac_fifo_name CONFIG.AXI_SIZE 5 -ad_ip_parameter $dac_fifo_name CONFIG.AXI_LENGTH 255 -ad_ip_parameter $dac_fifo_name CONFIG.AXI_ADDRESS 0x80000000 +ad_data_offload_create axi_tx_offload_control \ + 1 \ + 1 \ + [expr 2 * 1024 * 1024 * 1024] \ + [expr 32*$TX_NUM_OF_LANES] \ + [expr 32*$TX_NUM_OF_LANES] \ + 256 \ + 31 -create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_1_rstgen -ad_connect ddr4_1_rstgen/slowest_sync_clk ddr4_1/c0_ddr4_ui_clk -ad_connect ddr4_1/c0_ddr4_ui_clk_sync_rst ddr4_1_rstgen/ext_reset_in -ad_connect ddr4_1_rstgen/peripheral_aresetn axi_tx_fifo/axi_resetn +ad_ip_instance proc_sys_reset axi_tx_offload_rstgen +ad_connect axi_tx_offload_rstgen/slowest_sync_clk ddr4_tx_offload/c0_ddr4_ui_clk +ad_connect ddr4_tx_offload/c0_ddr4_ui_clk_sync_rst axi_tx_offload_rstgen/ext_reset_in +ad_connect ddr4_tx_offload/c0_ddr4_ui_clk axi_tx_offload_control/fifo2axi_bridge/axi_clk +ad_connect axi_tx_offload_rstgen/peripheral_aresetn axi_tx_offload_control/fifo2axi_bridge/axi_resetn +ad_connect ddr4_tx_offload/C0_DDR4_S_AXI axi_tx_offload_control/fifo2axi_bridge/ddr_axi +ad_connect sys_rstgen/peripheral_reset ddr4_tx_offload/sys_rst -ad_connect sys_reset ddr4_1/sys_rst +assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells ddr4_tx_offload]] -source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +# PL side DDR4 controller with RX data offload instance - 8 GByte + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_if_rx_offload +create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_ref_clk_rx_offload + +ad_ip_instance ip:ddr4 ddr4_rx_offload +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_DataWidth {32} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_AxiDataWidth {256} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_AxiAddressWidth {31} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_InputClockPeriod {3334} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.BANK_GROUP_WIDTH {1} +ad_ip_parameter ddr4_rx_offload CONFIG.C0.DDR4_CasLatency {18} + +ad_connect ddr4_if_rx_offload ddr4_rx_offload/C0_DDR4 + +set_property -dict [list CONFIG.FREQ_HZ {300000000}] [get_bd_intf_ports ddr4_ref_clk_rx_offload] +ad_connect ddr4_ref_clk_rx_offload ddr4_rx_offload/C0_SYS_CLK + +ad_data_offload_create axi_rx_offload_control \ + 0 \ + 1 \ + [expr 2 * 1024 * 1024 * 1024] \ + [expr 32*$RX_NUM_OF_LANES] \ + [expr 32*$RX_NUM_OF_LANES] \ + 256 \ + 31 + +ad_ip_instance proc_sys_reset axi_rx_offload_rstgen +ad_connect axi_rx_offload_rstgen/slowest_sync_clk ddr4_rx_offload/c0_ddr4_ui_clk +ad_connect ddr4_rx_offload/c0_ddr4_ui_clk_sync_rst axi_rx_offload_rstgen/ext_reset_in +ad_connect ddr4_rx_offload/c0_ddr4_ui_clk axi_rx_offload_control/fifo2axi_bridge/axi_clk +ad_connect axi_rx_offload_rstgen/peripheral_aresetn axi_rx_offload_control/fifo2axi_bridge/axi_resetn +ad_connect ddr4_rx_offload/C0_DDR4_S_AXI axi_rx_offload_control/fifo2axi_bridge/ddr_axi +ad_connect sys_rstgen/peripheral_reset ddr4_rx_offload/sys_rst + +assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells ddr4_rx_offload]] + +# JESD204 components ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES @@ -250,7 +292,7 @@ ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.CYCLIC 1 ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_SLICE_SRC 1 ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width +ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr 32 * $TX_NUM_OF_LANES] ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_instance axi_adxcvr axi_adrv9009_som_rx_xcvr @@ -272,7 +314,7 @@ adi_tpl_jesd204_rx_create rx_adrv9009_som_tpl_core $RX_NUM_OF_LANES \ $RX_SAMPLE_WIDTH ad_ip_instance axi_dmac axi_adrv9009_som_rx_dma -ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_TYPE_SRC 1 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.SYNC_TRANSFER_START 1 @@ -412,29 +454,38 @@ for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} { ad_connect obs_adrv9009_som_tpl_core/adc_data_$i util_som_obs_cpack/fifo_wr_data_$i } ad_connect obs_adrv9009_som_tpl_core/adc_dovf util_som_obs_cpack/fifo_wr_overflow -ad_connect util_som_obs_cpack/packed_fifo_wr axi_adrv9009_som_obs_dma/fifo_wr -ad_connect core_clk_a axi_adrv9009_som_tx_dma/m_axis_aclk +ad_connect sys_cpu_clk axi_tx_offload_control/s_axi_aclk +ad_connect core_clk_a axi_tx_offload_control/m_axis_aclk +ad_connect sys_dma_clk axi_tx_offload_control/s_axis_aclk +ad_connect sys_dma_clk axi_adrv9009_som_tx_dma/m_axis_aclk -ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b -ad_connect util_som_rx_cpack/packed_fifo_wr axi_adrv9009_som_rx_dma/fifo_wr +ad_connect sys_cpu_resetn axi_tx_offload_control/s_axi_aresetn +ad_connect core_clk_a_rstgen/peripheral_aresetn axi_tx_offload_control/m_axis_aresetn +ad_connect sys_dma_resetn axi_tx_offload_control/s_axis_aresetn -ad_connect axi_tx_fifo/axi ddr4_1/C0_DDR4_S_AXI -ad_connect ddr4_1/c0_ddr4_aresetn ddr4_1_rstgen/peripheral_aresetn -ad_connect core_clk_a axi_tx_fifo/dma_clk -ad_connect axi_tx_fifo/dma_rst core_clk_a_rstgen/peripheral_reset -ad_connect axi_tx_fifo/dma_valid axi_adrv9009_som_tx_dma/m_axis_valid -ad_connect axi_tx_fifo/dma_ready axi_adrv9009_som_tx_dma/m_axis_ready -ad_connect axi_adrv9009_som_tx_dma/m_axis_data axi_tx_fifo/dma_data -ad_connect axi_adrv9009_som_tx_dma/m_axis_last axi_tx_fifo/dma_xfer_last -ad_connect axi_adrv9009_som_tx_dma/m_axis_xfer_req axi_tx_fifo/dma_xfer_req -ad_connect core_clk_a axi_tx_fifo/dac_clk -ad_connect axi_tx_fifo/dac_rst core_clk_a_rstgen/peripheral_reset -ad_connect util_som_tx_upack/s_axis_data axi_tx_fifo/dac_data -ad_connect util_som_tx_upack/s_axis_ready axi_tx_fifo/dac_valid -ad_connect axi_tx_fifo/axi_clk ddr4_1/c0_ddr4_ui_clk -ad_connect dac_fifo_bypass axi_tx_fifo/bypass -ad_connect util_som_tx_upack/s_axis_valid VCC_1/dout +ad_connect sys_cpu_clk axi_rx_offload_control/s_axi_aclk +ad_connect core_clk_b axi_rx_offload_control/s_axis_aclk +ad_connect sys_dma_clk axi_rx_offload_control/m_axis_aclk +ad_connect sys_dma_clk axi_adrv9009_som_rx_dma/s_axis_aclk + +ad_connect sys_cpu_resetn axi_rx_offload_control/s_axi_aresetn +ad_connect core_clk_b_rstgen/peripheral_aresetn axi_rx_offload_control/s_axis_aresetn +ad_connect sys_dma_resetn axi_rx_offload_control/m_axis_aresetn + +ad_connect util_som_tx_upack/s_axis axi_tx_offload_control/m_axis +ad_connect axi_tx_offload_control/s_axis axi_adrv9009_som_tx_dma/m_axis +ad_connect axi_tx_offload_control/init_req axi_adrv9009_som_tx_dma/m_axis_xfer_req +ad_connect axi_tx_offload_control/sync_ext GND + +ad_connect util_som_rx_cpack/packed_fifo_wr_en axi_rx_offload_control/s_axis_tvalid +ad_connect util_som_rx_cpack/packed_fifo_wr_data axi_rx_offload_control/s_axis_tdata +ad_connect axi_rx_offload_control/m_axis axi_adrv9009_som_rx_dma/s_axis +ad_connect axi_rx_offload_control/init_req axi_adrv9009_som_rx_dma/s_axis_xfer_req +ad_connect axi_rx_offload_control/sync_ext GND + +## NOTE: software reconfigurable +## ad_connect dac_fifo_bypass axi_tx_fifo/bypass ad_ip_instance clk_wiz dma_clk_wiz ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM @@ -469,6 +520,8 @@ ad_cpu_interconnect 0x7c400000 axi_adrv9009_som_tx_dma ad_cpu_interconnect 0x7c420000 axi_adrv9009_som_rx_dma ad_cpu_interconnect 0x7c440000 axi_adrv9009_som_obs_dma ad_cpu_interconnect 0x45000000 axi_sysid_0 +ad_cpu_interconnect 0x7c480000 axi_tx_offload_control +ad_cpu_interconnect 0x7c4C0000 axi_rx_offload_control # gt uses hp0, and 100MHz clock for both DRP and AXI4 @@ -511,5 +564,5 @@ create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \ [get_bd_addr_spaces axi_adrv9009_som_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] SEG_sys_ps8_HP2_DDR_LOW create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \ [get_bd_addr_spaces axi_adrv9009_som_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_LOW] SEG_sys_ps8_HP3_DDR_LOW -create_bd_addr_seg -range 0x80000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_tx_fifo/axi] [get_bd_addr_segs ddr4_1/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_1_C0_DDR4_ADDRESS_BLOCK +#create_bd_addr_seg -range 0x80000000 -offset 0x80000000 \ +# [get_bd_addr_spaces axi_tx_fifo/axi] [get_bd_addr_segs ddr4_1/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_1_C0_DDR4_ADDRESS_BLOCK diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_constr.xdc b/projects/adrv9009zu11eg/common/adrv9009zu11eg_constr.xdc index cc800de01..04c0ee25f 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_constr.xdc +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_constr.xdc @@ -1,74 +1,144 @@ -set_property PACKAGE_PIN G24 [get_ports {ddr4_rtl_1_adr[0]}] -set_property PACKAGE_PIN G25 [get_ports {ddr4_rtl_1_adr[1]}] -set_property PACKAGE_PIN G20 [get_ports {ddr4_rtl_1_adr[2]}] -set_property PACKAGE_PIN G21 [get_ports {ddr4_rtl_1_adr[3]}] -set_property PACKAGE_PIN J24 [get_ports {ddr4_rtl_1_adr[4]}] -set_property PACKAGE_PIN H24 [get_ports {ddr4_rtl_1_adr[5]}] -set_property PACKAGE_PIN J21 [get_ports {ddr4_rtl_1_adr[6]}] -set_property PACKAGE_PIN H21 [get_ports {ddr4_rtl_1_adr[7]}] -set_property PACKAGE_PIN J22 [get_ports {ddr4_rtl_1_adr[8]}] -set_property PACKAGE_PIN H22 [get_ports {ddr4_rtl_1_adr[9]}] -set_property PACKAGE_PIN J20 [get_ports {ddr4_rtl_1_adr[10]}] -set_property PACKAGE_PIN N21 [get_ports {ddr4_rtl_1_adr[11]}] -set_property PACKAGE_PIN M21 [get_ports {ddr4_rtl_1_adr[12]}] -set_property PACKAGE_PIN K23 [get_ports {ddr4_rtl_1_adr[13]}] -set_property PACKAGE_PIN K24 [get_ports {ddr4_rtl_1_adr[14]}] -set_property PACKAGE_PIN L21 [get_ports {ddr4_rtl_1_adr[15]}] -set_property PACKAGE_PIN M20 [get_ports {ddr4_rtl_1_adr[16]}] -set_property PACKAGE_PIN E20 [get_ports {ddr4_rtl_1_dq[0]}] -set_property PACKAGE_PIN D16 [get_ports {ddr4_rtl_1_dq[1]}] -set_property PACKAGE_PIN G18 [get_ports {ddr4_rtl_1_dq[2]}] -set_property PACKAGE_PIN E17 [get_ports {ddr4_rtl_1_dq[3]}] -set_property PACKAGE_PIN G19 [get_ports {ddr4_rtl_1_dq[4]}] -set_property PACKAGE_PIN F18 [get_ports {ddr4_rtl_1_dq[5]}] -set_property PACKAGE_PIN F20 [get_ports {ddr4_rtl_1_dq[6]}] -set_property PACKAGE_PIN D17 [get_ports {ddr4_rtl_1_dq[7]}] -set_property PACKAGE_PIN B19 [get_ports {ddr4_rtl_1_dq[8]}] -set_property PACKAGE_PIN A16 [get_ports {ddr4_rtl_1_dq[9]}] -set_property PACKAGE_PIN B20 [get_ports {ddr4_rtl_1_dq[10]}] -set_property PACKAGE_PIN C17 [get_ports {ddr4_rtl_1_dq[11]}] -set_property PACKAGE_PIN A20 [get_ports {ddr4_rtl_1_dq[12]}] -set_property PACKAGE_PIN B16 [get_ports {ddr4_rtl_1_dq[13]}] -set_property PACKAGE_PIN B18 [get_ports {ddr4_rtl_1_dq[14]}] -set_property PACKAGE_PIN C16 [get_ports {ddr4_rtl_1_dq[15]}] -set_property PACKAGE_PIN B25 [get_ports {ddr4_rtl_1_dq[16]}] -set_property PACKAGE_PIN C21 [get_ports {ddr4_rtl_1_dq[17]}] -set_property PACKAGE_PIN B24 [get_ports {ddr4_rtl_1_dq[18]}] -set_property PACKAGE_PIN C22 [get_ports {ddr4_rtl_1_dq[19]}] -set_property PACKAGE_PIN B26 [get_ports {ddr4_rtl_1_dq[20]}] -set_property PACKAGE_PIN A21 [get_ports {ddr4_rtl_1_dq[21]}] -set_property PACKAGE_PIN B21 [get_ports {ddr4_rtl_1_dq[23]}] -set_property PACKAGE_PIN B23 [get_ports {ddr4_rtl_1_dq[22]}] -set_property PACKAGE_PIN E23 [get_ports {ddr4_rtl_1_dq[24]}] -set_property PACKAGE_PIN F21 [get_ports {ddr4_rtl_1_dq[25]}] -set_property PACKAGE_PIN F23 [get_ports {ddr4_rtl_1_dq[26]}] -set_property PACKAGE_PIN F22 [get_ports {ddr4_rtl_1_dq[27]}] -set_property PACKAGE_PIN E25 [get_ports {ddr4_rtl_1_dq[28]}] -set_property PACKAGE_PIN D22 [get_ports {ddr4_rtl_1_dq[29]}] -set_property PACKAGE_PIN F25 [get_ports {ddr4_rtl_1_dq[30]}] -set_property PACKAGE_PIN D21 [get_ports {ddr4_rtl_1_dq[31]}] -set_property PACKAGE_PIN E19 [get_ports {ddr4_rtl_1_dqs_t[0]}] -set_property PACKAGE_PIN A18 [get_ports {ddr4_rtl_1_dqs_t[1]}] -set_property PACKAGE_PIN A25 [get_ports {ddr4_rtl_1_dqs_t[2]}] -set_property PACKAGE_PIN D24 [get_ports {ddr4_rtl_1_dqs_t[3]}] -set_property PACKAGE_PIN L22 [get_ports {ddr4_rtl_1_ba[0]}] -set_property PACKAGE_PIN L23 [get_ports {ddr4_rtl_1_ba[1]}] -set_property PACKAGE_PIN L20 [get_ports {ddr4_rtl_1_bg[0]}] -set_property PACKAGE_PIN N22 [get_ports {ddr4_rtl_1_ck_t[0]}] -set_property PACKAGE_PIN D25 [get_ports {ddr4_rtl_1_odt[0]}] -set_property PACKAGE_PIN F17 [get_ports {ddr4_rtl_1_dm_n[0]}] -set_property PACKAGE_PIN C19 [get_ports {ddr4_rtl_1_dm_n[1]}] -set_property PACKAGE_PIN A22 [get_ports {ddr4_rtl_1_dm_n[2]}] -set_property PACKAGE_PIN E24 [get_ports {ddr4_rtl_1_dm_n[3]}] -set_property PACKAGE_PIN A23 [get_ports {ddr4_rtl_1_cs_n[0]}] -set_property PACKAGE_PIN E22 [get_ports ddr4_rtl_1_act_n] -set_property PACKAGE_PIN K22 [get_ports {ddr4_rtl_1_cke[0]}] -set_property PACKAGE_PIN D20 [get_ports ddr4_rtl_1_reset_n] +set_property PACKAGE_PIN G24 [get_ports {ddr4_if_tx_offload_adr[0]}] +set_property PACKAGE_PIN G25 [get_ports {ddr4_if_tx_offload_adr[1]}] +set_property PACKAGE_PIN G20 [get_ports {ddr4_if_tx_offload_adr[2]}] +set_property PACKAGE_PIN G21 [get_ports {ddr4_if_tx_offload_adr[3]}] +set_property PACKAGE_PIN J24 [get_ports {ddr4_if_tx_offload_adr[4]}] +set_property PACKAGE_PIN H24 [get_ports {ddr4_if_tx_offload_adr[5]}] +set_property PACKAGE_PIN J21 [get_ports {ddr4_if_tx_offload_adr[6]}] +set_property PACKAGE_PIN H21 [get_ports {ddr4_if_tx_offload_adr[7]}] +set_property PACKAGE_PIN J22 [get_ports {ddr4_if_tx_offload_adr[8]}] +set_property PACKAGE_PIN H22 [get_ports {ddr4_if_tx_offload_adr[9]}] +set_property PACKAGE_PIN J20 [get_ports {ddr4_if_tx_offload_adr[10]}] +set_property PACKAGE_PIN N21 [get_ports {ddr4_if_tx_offload_adr[11]}] +set_property PACKAGE_PIN M21 [get_ports {ddr4_if_tx_offload_adr[12]}] +set_property PACKAGE_PIN K23 [get_ports {ddr4_if_tx_offload_adr[13]}] +set_property PACKAGE_PIN K24 [get_ports {ddr4_if_tx_offload_adr[14]}] +set_property PACKAGE_PIN L21 [get_ports {ddr4_if_tx_offload_adr[15]}] +set_property PACKAGE_PIN M20 [get_ports {ddr4_if_tx_offload_adr[16]}] +set_property PACKAGE_PIN E20 [get_ports {ddr4_if_tx_offload_dq[0]}] +set_property PACKAGE_PIN D16 [get_ports {ddr4_if_tx_offload_dq[1]}] +set_property PACKAGE_PIN G18 [get_ports {ddr4_if_tx_offload_dq[2]}] +set_property PACKAGE_PIN E17 [get_ports {ddr4_if_tx_offload_dq[3]}] +set_property PACKAGE_PIN G19 [get_ports {ddr4_if_tx_offload_dq[4]}] +set_property PACKAGE_PIN F18 [get_ports {ddr4_if_tx_offload_dq[5]}] +set_property PACKAGE_PIN F20 [get_ports {ddr4_if_tx_offload_dq[6]}] +set_property PACKAGE_PIN D17 [get_ports {ddr4_if_tx_offload_dq[7]}] +set_property PACKAGE_PIN B19 [get_ports {ddr4_if_tx_offload_dq[8]}] +set_property PACKAGE_PIN A16 [get_ports {ddr4_if_tx_offload_dq[9]}] +set_property PACKAGE_PIN B20 [get_ports {ddr4_if_tx_offload_dq[10]}] +set_property PACKAGE_PIN C17 [get_ports {ddr4_if_tx_offload_dq[11]}] +set_property PACKAGE_PIN A20 [get_ports {ddr4_if_tx_offload_dq[12]}] +set_property PACKAGE_PIN B16 [get_ports {ddr4_if_tx_offload_dq[13]}] +set_property PACKAGE_PIN B18 [get_ports {ddr4_if_tx_offload_dq[14]}] +set_property PACKAGE_PIN C16 [get_ports {ddr4_if_tx_offload_dq[15]}] +set_property PACKAGE_PIN B25 [get_ports {ddr4_if_tx_offload_dq[16]}] +set_property PACKAGE_PIN C21 [get_ports {ddr4_if_tx_offload_dq[17]}] +set_property PACKAGE_PIN B24 [get_ports {ddr4_if_tx_offload_dq[18]}] +set_property PACKAGE_PIN C22 [get_ports {ddr4_if_tx_offload_dq[19]}] +set_property PACKAGE_PIN B26 [get_ports {ddr4_if_tx_offload_dq[20]}] +set_property PACKAGE_PIN A21 [get_ports {ddr4_if_tx_offload_dq[21]}] +set_property PACKAGE_PIN B21 [get_ports {ddr4_if_tx_offload_dq[23]}] +set_property PACKAGE_PIN B23 [get_ports {ddr4_if_tx_offload_dq[22]}] +set_property PACKAGE_PIN E23 [get_ports {ddr4_if_tx_offload_dq[24]}] +set_property PACKAGE_PIN F21 [get_ports {ddr4_if_tx_offload_dq[25]}] +set_property PACKAGE_PIN F23 [get_ports {ddr4_if_tx_offload_dq[26]}] +set_property PACKAGE_PIN F22 [get_ports {ddr4_if_tx_offload_dq[27]}] +set_property PACKAGE_PIN E25 [get_ports {ddr4_if_tx_offload_dq[28]}] +set_property PACKAGE_PIN D22 [get_ports {ddr4_if_tx_offload_dq[29]}] +set_property PACKAGE_PIN F25 [get_ports {ddr4_if_tx_offload_dq[30]}] +set_property PACKAGE_PIN D21 [get_ports {ddr4_if_tx_offload_dq[31]}] +set_property PACKAGE_PIN E19 [get_ports {ddr4_if_tx_offload_dqs_t[0]}] +set_property PACKAGE_PIN A18 [get_ports {ddr4_if_tx_offload_dqs_t[1]}] +set_property PACKAGE_PIN A25 [get_ports {ddr4_if_tx_offload_dqs_t[2]}] +set_property PACKAGE_PIN D24 [get_ports {ddr4_if_tx_offload_dqs_t[3]}] +set_property PACKAGE_PIN L22 [get_ports {ddr4_if_tx_offload_ba[0]}] +set_property PACKAGE_PIN L23 [get_ports {ddr4_if_tx_offload_ba[1]}] +set_property PACKAGE_PIN L20 [get_ports {ddr4_if_tx_offload_bg[0]}] +set_property PACKAGE_PIN N22 [get_ports {ddr4_if_tx_offload_ck_t[0]}] +set_property PACKAGE_PIN D25 [get_ports {ddr4_if_tx_offload_odt[0]}] +set_property PACKAGE_PIN F17 [get_ports {ddr4_if_tx_offload_dm_n[0]}] +set_property PACKAGE_PIN C19 [get_ports {ddr4_if_tx_offload_dm_n[1]}] +set_property PACKAGE_PIN A22 [get_ports {ddr4_if_tx_offload_dm_n[2]}] +set_property PACKAGE_PIN E24 [get_ports {ddr4_if_tx_offload_dm_n[3]}] +set_property PACKAGE_PIN A23 [get_ports {ddr4_if_tx_offload_cs_n[0]}] +set_property PACKAGE_PIN E22 [get_ports ddr4_if_tx_offload_act_n] +set_property PACKAGE_PIN K22 [get_ports {ddr4_if_tx_offload_cke[0]}] +set_property PACKAGE_PIN D20 [get_ports ddr4_if_tx_offload_reset_n] -set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVDS} [get_ports ddr4_ref_1_clk_p] -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_par] -set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_alert_n] +set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVDS} [get_ports ddr4_ref_clk_tx_offload_p] +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS12} [get_ports ddr4_if_tx_offload_par] +set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS12} [get_ports ddr4_if_tx_offload_alert_n] + +set_property PACKAGE_PIN C31 [get_ports {ddr4_if_rx_offload_adr[0]}] +set_property PACKAGE_PIN B31 [get_ports {ddr4_if_rx_offload_adr[1]}] +set_property PACKAGE_PIN A27 [get_ports {ddr4_if_rx_offload_adr[2]}] +set_property PACKAGE_PIN A28 [get_ports {ddr4_if_rx_offload_adr[3]}] +set_property PACKAGE_PIN A30 [get_ports {ddr4_if_rx_offload_adr[4]}] +set_property PACKAGE_PIN A31 [get_ports {ddr4_if_rx_offload_adr[5]}] +set_property PACKAGE_PIN C28 [get_ports {ddr4_if_rx_offload_adr[6]}] +set_property PACKAGE_PIN C29 [get_ports {ddr4_if_rx_offload_adr[7]}] +set_property PACKAGE_PIN B29 [get_ports {ddr4_if_rx_offload_adr[8]}] +set_property PACKAGE_PIN B30 [get_ports {ddr4_if_rx_offload_adr[9]}] +set_property PACKAGE_PIN C27 [get_ports {ddr4_if_rx_offload_adr[10]}] +set_property PACKAGE_PIN B28 [get_ports {ddr4_if_rx_offload_adr[11]}] +set_property PACKAGE_PIN F30 [get_ports {ddr4_if_rx_offload_adr[12]}] +set_property PACKAGE_PIN F31 [get_ports {ddr4_if_rx_offload_adr[13]}] +set_property PACKAGE_PIN E29 [get_ports {ddr4_if_rx_offload_adr[14]}] +set_property PACKAGE_PIN D29 [get_ports {ddr4_if_rx_offload_adr[15]}] +set_property PACKAGE_PIN E30 [get_ports {ddr4_if_rx_offload_adr[16]}] +set_property PACKAGE_PIN G30 [get_ports {ddr4_if_rx_offload_dq[0]}] +set_property PACKAGE_PIN F26 [get_ports {ddr4_if_rx_offload_dq[1]}] +set_property PACKAGE_PIN H28 [get_ports {ddr4_if_rx_offload_dq[2]}] +set_property PACKAGE_PIN G26 [get_ports {ddr4_if_rx_offload_dq[3]}] +set_property PACKAGE_PIN H29 [get_ports {ddr4_if_rx_offload_dq[4]}] +set_property PACKAGE_PIN J27 [get_ports {ddr4_if_rx_offload_dq[5]}] +set_property PACKAGE_PIN G31 [get_ports {ddr4_if_rx_offload_dq[6]}] +set_property PACKAGE_PIN J26 [get_ports {ddr4_if_rx_offload_dq[7]}] +set_property PACKAGE_PIN M25 [get_ports {ddr4_if_rx_offload_dq[8]}] +set_property PACKAGE_PIN L27 [get_ports {ddr4_if_rx_offload_dq[9]}] +set_property PACKAGE_PIN J25 [get_ports {ddr4_if_rx_offload_dq[10]}] +set_property PACKAGE_PIN K28 [get_ports {ddr4_if_rx_offload_dq[11]}] +set_property PACKAGE_PIN L25 [get_ports {ddr4_if_rx_offload_dq[12]}] +set_property PACKAGE_PIN J29 [get_ports {ddr4_if_rx_offload_dq[13]}] +set_property PACKAGE_PIN K25 [get_ports {ddr4_if_rx_offload_dq[14]}] +set_property PACKAGE_PIN L28 [get_ports {ddr4_if_rx_offload_dq[15]}] +set_property PACKAGE_PIN M18 [get_ports {ddr4_if_rx_offload_dq[16]}] +set_property PACKAGE_PIN L15 [get_ports {ddr4_if_rx_offload_dq[17]}] +set_property PACKAGE_PIN L18 [get_ports {ddr4_if_rx_offload_dq[18]}] +set_property PACKAGE_PIN M16 [get_ports {ddr4_if_rx_offload_dq[19]}] +set_property PACKAGE_PIN N19 [get_ports {ddr4_if_rx_offload_dq[20]}] +set_property PACKAGE_PIN M15 [get_ports {ddr4_if_rx_offload_dq[21]}] +set_property PACKAGE_PIN N18 [get_ports {ddr4_if_rx_offload_dq[22]}] +set_property PACKAGE_PIN N16 [get_ports {ddr4_if_rx_offload_dq[23]}] +set_property PACKAGE_PIN K17 [get_ports {ddr4_if_rx_offload_dq[24]}] +set_property PACKAGE_PIN G16 [get_ports {ddr4_if_rx_offload_dq[25]}] +set_property PACKAGE_PIN H18 [get_ports {ddr4_if_rx_offload_dq[26]}] +set_property PACKAGE_PIN H17 [get_ports {ddr4_if_rx_offload_dq[27]}] +set_property PACKAGE_PIN J17 [get_ports {ddr4_if_rx_offload_dq[28]}] +set_property PACKAGE_PIN H16 [get_ports {ddr4_if_rx_offload_dq[29]}] +set_property PACKAGE_PIN H19 [get_ports {ddr4_if_rx_offload_dq[30]}] +set_property PACKAGE_PIN J16 [get_ports {ddr4_if_rx_offload_dq[31]}] +set_property PACKAGE_PIN H26 [get_ports {ddr4_if_rx_offload_dqs_t[0]}] +set_property PACKAGE_PIN M26 [get_ports {ddr4_if_rx_offload_dqs_t[1]}] +set_property PACKAGE_PIN L17 [get_ports {ddr4_if_rx_offload_dqs_t[2]}] +set_property PACKAGE_PIN K19 [get_ports {ddr4_if_rx_offload_dqs_t[3]}] +set_property PACKAGE_PIN D30 [get_ports {ddr4_if_rx_offload_ba[0]}] +set_property PACKAGE_PIN D26 [get_ports {ddr4_if_rx_offload_ba[1]}] +set_property PACKAGE_PIN D27 [get_ports {ddr4_if_rx_offload_bg[0]}] +set_property PACKAGE_PIN E27 [get_ports {ddr4_if_rx_offload_ck_t[0]}] +set_property PACKAGE_PIN D31 [get_ports {ddr4_if_rx_offload_odt[0]}] +set_property PACKAGE_PIN G28 [get_ports {ddr4_if_rx_offload_dm_n[0]}] +set_property PACKAGE_PIN K29 [get_ports {ddr4_if_rx_offload_dm_n[1]}] +set_property PACKAGE_PIN N14 [get_ports {ddr4_if_rx_offload_dm_n[2]}] +set_property PACKAGE_PIN K15 [get_ports {ddr4_if_rx_offload_dm_n[3]}] +set_property PACKAGE_PIN G29 [get_ports {ddr4_if_rx_offload_cs_n[0]}] +set_property PACKAGE_PIN J30 [get_ports ddr4_if_rx_offload_act_n] +set_property PACKAGE_PIN K30 [get_ports {ddr4_if_rx_offload_cke[0]}] +set_property PACKAGE_PIN M14 [get_ports ddr4_if_rx_offload_reset_n] +set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS12} [get_ports ddr4_if_rx_offload_par] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS12} [get_ports ddr4_if_rx_offload_alert_n] +set_property -dict {PACKAGE_PIN F27 IOSTANDARD LVDS} [get_ports ddr4_ref_clk_rx_offload_p] set_property PACKAGE_PIN N12 [get_ports ref_clk_a_p]; set_property PACKAGE_PIN N11 [get_ports ref_clk_a_n];