axi_ad9434: Update the core to the new DRP interface
Istvan Csomortani
parent
913eafed48
commit
781702c1b9
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@ -167,8 +167,8 @@ module axi_ad9434 (
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire [31:0] up_drp_wdata_s;
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wire [31:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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@ -109,8 +109,8 @@ module axi_ad9434_core (
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output up_drp_sel;
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output up_drp_wr;
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output [11:0] up_drp_addr;
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output [15:0] up_drp_wdata;
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input [15:0] up_drp_rdata;
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output [31:0] up_drp_wdata;
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input [31:0] up_drp_rdata;
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input up_drp_ready;
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input up_drp_locked;
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@ -124,8 +124,8 @@ module axi_ad9434_if (
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input up_drp_sel;
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input up_drp_wr;
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input [11:0] up_drp_addr;
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input [15:0] up_drp_wdata;
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output [15:0] up_drp_rdata;
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input [31:0] up_drp_wdata;
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output [31:0] up_drp_rdata;
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output up_drp_ready;
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output up_drp_locked;
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@ -147,37 +147,36 @@ module axi_ad9434_if (
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assign adc_clk = adc_div_clk;
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// data interface
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(SDR),
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.DATA_WIDTH(4))
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i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_data[(3*12)+l_inst]),
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.data_s1(adc_data[(2*12)+l_inst]),
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.data_s2(adc_data[(1*12)+l_inst]),
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.data_s3(adc_data[(0*12)+l_inst]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p[l_inst]),
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.data_in_n(adc_data_in_n[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[l_inst]),
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.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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end
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endgenerate
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ad_serdes_in #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.IODELAY_CTRL(0),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(SDR),
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.DATA_WIDTH(12))
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i_adc_data (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.loaden(1'b0),
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.phase(8'b0),
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.locked(1'b0),
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.data_s0(adc_data[47:36]),
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.data_s1(adc_data[35:24]),
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.data_s2(adc_data[23:12]),
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.data_s3(adc_data[11: 0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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.data_s7(),
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.data_in_p(adc_data_in_p),
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.data_in_n(adc_data_in_n),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[11:0]),
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.up_dwdata (up_adc_dwdata[59:0]),
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.up_drdata (up_adc_drdata[59:0]),
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.delay_clk(delay_clk),
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.delay_rst(delay_rst),
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.delay_locked());
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// over-range interface
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ad_serdes_in #(
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@ -185,15 +184,18 @@ module axi_ad9434_if (
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.IODELAY_CTRL(1),
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.IODELAY_GROUP(IO_DELAY_GROUP),
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.DDR_OR_SDR_N(SDR),
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.DATA_WIDTH(4))
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i_adc_data (
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.DATA_WIDTH(1))
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i_adc_or (
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.rst(adc_rst),
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.clk(adc_clk_in),
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.div_clk(adc_div_clk),
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.data_s0(adc_or_s[0]),
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.data_s1(adc_or_s[1]),
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.data_s2(adc_or_s[2]),
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.data_s3(adc_or_s[3]),
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.loaden(1'b0),
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.phase(8'b0),
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.locked(1'b0),
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.data_s0(adc_or_s[3]),
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.data_s1(adc_or_s[2]),
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.data_s2(adc_or_s[1]),
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.data_s3(adc_or_s[0]),
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.data_s4(),
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.data_s5(),
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.data_s6(),
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@ -210,19 +212,21 @@ module axi_ad9434_if (
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// clock input buffers and MMCM_OR_BUFR_N
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ad_serdes_clk #(
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.MMCM_DEVICE_TYPE (DEVICE_TYPE),
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.DEVICE_TYPE (DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (2),
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.MMCM_VCO_DIV (6),
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.MMCM_VCO_MUL (12),
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.MMCM_CLK0_DIV (2),
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.MMCM_CLK1_DIV (8))
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i_serdes_clk (
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.mmcm_rst (mmcm_rst),
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.rst (mmcm_rst),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk_in),
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.div_clk (adc_div_clk),
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.out_clk (),
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.loaden (),
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.phase (),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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@ -233,7 +237,7 @@ module axi_ad9434_if (
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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// adc overange
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// adc over range
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assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
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// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
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