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axi_ad9434: Update the core to the new DRP interface

main
Istvan Csomortani 2016-09-21 15:12:59 +03:00
parent 913eafed48
commit 781702c1b9
3 changed files with 50 additions and 46 deletions
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4
library/axi_ad9434/axi_ad9434.v
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@ -167,8 +167,8 @@ module axi_ad9434 (
wire up_drp_sel_s; wire up_drp_sel_s;
wire up_drp_wr_s; wire up_drp_wr_s;
wire [11:0] up_drp_addr_s; wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s; wire [31:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s; wire [31:0] up_drp_rdata_s;
wire up_drp_ready_s; wire up_drp_ready_s;
wire up_drp_locked_s; wire up_drp_locked_s;

4
library/axi_ad9434/axi_ad9434_core.v
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@ -109,8 +109,8 @@ module axi_ad9434_core (
output up_drp_sel; output up_drp_sel;
output up_drp_wr; output up_drp_wr;
output [11:0] up_drp_addr; output [11:0] up_drp_addr;
output [15:0] up_drp_wdata; output [31:0] up_drp_wdata;
input [15:0] up_drp_rdata; input [31:0] up_drp_rdata;
input up_drp_ready; input up_drp_ready;
input up_drp_locked; input up_drp_locked;

88
library/axi_ad9434/axi_ad9434_if.v
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@ -124,8 +124,8 @@ module axi_ad9434_if (
input up_drp_sel; input up_drp_sel;
input up_drp_wr; input up_drp_wr;
input [11:0] up_drp_addr; input [11:0] up_drp_addr;
input [15:0] up_drp_wdata; input [31:0] up_drp_wdata;
output [15:0] up_drp_rdata; output [31:0] up_drp_rdata;
output up_drp_ready; output up_drp_ready;
output up_drp_locked; output up_drp_locked;
@ -147,37 +147,36 @@ module axi_ad9434_if (
assign adc_clk = adc_div_clk; assign adc_clk = adc_div_clk;
// data interface // data interface
generate ad_serdes_in #(
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if .DEVICE_TYPE(DEVICE_TYPE),
ad_serdes_in #( .IODELAY_CTRL(0),
.DEVICE_TYPE(DEVICE_TYPE), .IODELAY_GROUP(IO_DELAY_GROUP),
.IODELAY_CTRL(0), .DDR_OR_SDR_N(SDR),
.IODELAY_GROUP(IO_DELAY_GROUP), .DATA_WIDTH(12))
.DDR_OR_SDR_N(SDR), i_adc_data (
.DATA_WIDTH(4)) .rst(adc_rst),
i_adc_data ( .clk(adc_clk_in),
.rst(adc_rst), .div_clk(adc_div_clk),
.clk(adc_clk_in), .loaden(1'b0),
.div_clk(adc_div_clk), .phase(8'b0),
.data_s0(adc_data[(3*12)+l_inst]), .locked(1'b0),
.data_s1(adc_data[(2*12)+l_inst]), .data_s0(adc_data[47:36]),
.data_s2(adc_data[(1*12)+l_inst]), .data_s1(adc_data[35:24]),
.data_s3(adc_data[(0*12)+l_inst]), .data_s2(adc_data[23:12]),
.data_s4(), .data_s3(adc_data[11: 0]),
.data_s5(), .data_s4(),
.data_s6(), .data_s5(),
.data_s7(), .data_s6(),
.data_in_p(adc_data_in_p[l_inst]), .data_s7(),
.data_in_n(adc_data_in_n[l_inst]), .data_in_p(adc_data_in_p),
.up_clk (up_clk), .data_in_n(adc_data_in_n),
.up_dld (up_adc_dld[l_inst]), .up_clk (up_clk),
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), .up_dld (up_adc_dld[11:0]),
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), .up_dwdata (up_adc_dwdata[59:0]),
.delay_clk(delay_clk), .up_drdata (up_adc_drdata[59:0]),
.delay_rst(delay_rst), .delay_clk(delay_clk),
.delay_locked()); .delay_rst(delay_rst),
end .delay_locked());
endgenerate
// over-range interface // over-range interface
ad_serdes_in #( ad_serdes_in #(
@ -185,15 +184,18 @@ module axi_ad9434_if (
.IODELAY_CTRL(1), .IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP), .IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(SDR), .DDR_OR_SDR_N(SDR),
.DATA_WIDTH(4)) .DATA_WIDTH(1))
i_adc_data ( i_adc_or (
.rst(adc_rst), .rst(adc_rst),
.clk(adc_clk_in), .clk(adc_clk_in),
.div_clk(adc_div_clk), .div_clk(adc_div_clk),
.data_s0(adc_or_s[0]), .loaden(1'b0),
.data_s1(adc_or_s[1]), .phase(8'b0),
.data_s2(adc_or_s[2]), .locked(1'b0),
.data_s3(adc_or_s[3]), .data_s0(adc_or_s[3]),
.data_s1(adc_or_s[2]),
.data_s2(adc_or_s[1]),
.data_s3(adc_or_s[0]),
.data_s4(), .data_s4(),
.data_s5(), .data_s5(),
.data_s6(), .data_s6(),
@ -210,19 +212,21 @@ module axi_ad9434_if (
// clock input buffers and MMCM_OR_BUFR_N // clock input buffers and MMCM_OR_BUFR_N
ad_serdes_clk #( ad_serdes_clk #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE), .DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (2), .MMCM_CLKIN_PERIOD (2),
.MMCM_VCO_DIV (6), .MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12), .MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2), .MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8)) .MMCM_CLK1_DIV (8))
i_serdes_clk ( i_serdes_clk (
.mmcm_rst (mmcm_rst), .rst (mmcm_rst),
.clk_in_p (adc_clk_in_p), .clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n), .clk_in_n (adc_clk_in_n),
.clk (adc_clk_in), .clk (adc_clk_in),
.div_clk (adc_div_clk), .div_clk (adc_div_clk),
.out_clk (), .out_clk (),
.loaden (),
.phase (),
.up_clk (up_clk), .up_clk (up_clk),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_drp_sel (up_drp_sel), .up_drp_sel (up_drp_sel),
@ -233,7 +237,7 @@ module axi_ad9434_if (
.up_drp_ready (up_drp_ready), .up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked)); .up_drp_locked (up_drp_locked));
// adc overange // adc over range
assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3]; assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3];
// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up