From 77631c871772afe4c2f36a970c5cc8a06347fc32 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 5 May 2017 18:55:49 +0200 Subject: [PATCH] axi_ad9250: Use the generic JESD204 ADC receiver core Replace the axi_ad9250 implementation with the new generic JESD204 interface ADC core. The replacement is functionally equivalent, except that the converter clock ratio is now correctly reported as 2 rather than 1 as before. Also the adc_rst output port is removed. It is not used in any design. The current guidelines for the reset for the JESD204 subsystem is to use an external reset generator. Signed-off-by: Lars-Peter Clausen --- library/axi_ad9250/Makefile | 35 ++-- library/axi_ad9250/axi_ad9250.v | 240 ++++-------------------- library/axi_ad9250/axi_ad9250_channel.v | 155 --------------- library/axi_ad9250/axi_ad9250_hw.tcl | 12 +- library/axi_ad9250/axi_ad9250_if.v | 115 ------------ library/axi_ad9250/axi_ad9250_ip.tcl | 22 +-- library/axi_ad9250/axi_ad9250_pnmon.v | 167 ----------------- 7 files changed, 69 insertions(+), 677 deletions(-) delete mode 100644 library/axi_ad9250/axi_ad9250_channel.v delete mode 100644 library/axi_ad9250/axi_ad9250_if.v delete mode 100644 library/axi_ad9250/axi_ad9250_pnmon.v diff --git a/library/axi_ad9250/Makefile b/library/axi_ad9250/Makefile index 1f316f7ad..301c6ed7e 100644 --- a/library/axi_ad9250/Makefile +++ b/library/axi_ad9250/Makefile @@ -5,31 +5,32 @@ LIBRARY_NAME := axi_ad9250 -GENERIC_DEPS += ../common/ad_datafmt.v -GENERIC_DEPS += ../common/ad_pnmon.v -GENERIC_DEPS += ../common/ad_rst.v -GENERIC_DEPS += ../common/ad_xcvr_rx_if.v -GENERIC_DEPS += ../common/up_adc_channel.v -GENERIC_DEPS += ../common/up_adc_common.v -GENERIC_DEPS += ../common/up_axi.v -GENERIC_DEPS += ../common/up_clock_mon.v -GENERIC_DEPS += ../common/up_xfer_cntrl.v -GENERIC_DEPS += ../common/up_xfer_status.v GENERIC_DEPS += axi_ad9250.v -GENERIC_DEPS += axi_ad9250_channel.v -GENERIC_DEPS += axi_ad9250_if.v -GENERIC_DEPS += axi_ad9250_pnmon.v -XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc -XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc -XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc -XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc XILINX_DEPS += axi_ad9250_ip.tcl +XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc + ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc ALTERA_DEPS += ../altera/common/up_rst_constr.sdc ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc +ALTERA_DEPS += ../common/ad_datafmt.v +ALTERA_DEPS += ../common/ad_pnmon.v +ALTERA_DEPS += ../common/ad_rst.v +ALTERA_DEPS += ../common/ad_xcvr_rx_if.v +ALTERA_DEPS += ../common/up_adc_channel.v +ALTERA_DEPS += ../common/up_adc_common.v +ALTERA_DEPS += ../common/up_axi.v +ALTERA_DEPS += ../common/up_clock_mon.v +ALTERA_DEPS += ../common/up_xfer_cntrl.v +ALTERA_DEPS += ../common/up_xfer_status.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v +ALTERA_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v ALTERA_DEPS += axi_ad9250_hw.tcl include ../scripts/library.mk diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 1fcad0281..b9b268f7d 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -51,7 +51,6 @@ module axi_ad9250 #( // dma interface output adc_clk, - output adc_rst, output adc_valid_a, output adc_enable_a, output [31:0] adc_data_a, @@ -84,209 +83,48 @@ module axi_ad9250 #( output [ 1:0] s_axi_rresp, input s_axi_rready); + assign adc_clk = rx_clk; - // internal registers + ad_ip_jesd204_tpl_adc #( + .ID (ID), + .NUM_LANES (2), + .NUM_CHANNELS (2), + .CHANNEL_WIDTH (14), + .TWOS_COMPLEMENT (1) + ) i_adc_jesd204 ( + .link_clk (rx_clk), - reg up_status_pn_err = 'd0; - reg up_status_pn_oos = 'd0; - reg up_status_or = 'd0; - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; + .link_sof (rx_sof), + .link_valid (rx_valid), + .link_data (rx_data), + .link_ready (rx_ready), - // internal clocks & resets + .enable ({adc_enable_b,adc_enable_a}), + .adc_valid ({adc_valid_b,adc_valid_a}), + .adc_data ({adc_data_b,adc_data_a}), + .adc_dovf (adc_dovf), - wire up_rstn; - wire up_clk; - - // internal signals - - wire [27:0] adc_data_a_s; - wire [27:0] adc_data_b_s; - wire adc_or_a_s; - wire adc_or_b_s; - wire adc_status_s; - wire [ 1:0] up_status_pn_err_s; - wire [ 1:0] up_status_pn_oos_s; - wire [ 1:0] up_status_or_s; - wire [31:0] up_rdata_s[0:2]; - wire up_rack_s[0:2]; - wire up_wack_s[0:2]; - wire up_wreq_s; - wire [13:0] up_waddr_s; - wire [31:0] up_wdata_s; - wire up_rreq_s; - wire [13:0] up_raddr_s; - - // signal name changes - - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; - - // defaults - - assign rx_ready = 1'b1; - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_status_pn_err <= 'd0; - up_status_pn_oos <= 'd0; - up_status_or <= 'd0; - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_status_pn_err <= | up_status_pn_err_s; - up_status_pn_oos <= | up_status_pn_oos_s; - up_status_or <= | up_status_or_s; - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; - end - end - - // adc valid - - assign adc_valid_a = 1'b1; - assign adc_valid_b = 1'b1; - - // main (device interface) - - axi_ad9250_if i_if ( - .rx_clk (rx_clk), - .rx_sof (rx_sof), - .rx_data (rx_data), - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data_a (adc_data_a_s), - .adc_data_b (adc_data_b_s), - .adc_or_a (adc_or_a_s), - .adc_or_b (adc_or_b_s), - .adc_status (adc_status_s)); - - // channel - - axi_ad9250_channel #(.CHANNEL_ID(0)) i_channel_0 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (adc_data_a_s), - .adc_or (adc_or_a_s), - .adc_dfmt_data (adc_data_a), - .adc_enable (adc_enable_a), - .up_adc_pn_err (up_status_pn_err_s[0]), - .up_adc_pn_oos (up_status_pn_oos_s[0]), - .up_adc_or (up_status_or_s[0]), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[0]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[0]), - .up_rack (up_rack_s[0])); - - // channel - - axi_ad9250_channel #(.CHANNEL_ID(1)) i_channel_1 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (adc_data_b_s), - .adc_or (adc_or_b_s), - .adc_dfmt_data (adc_data_b), - .adc_enable (adc_enable_b), - .up_adc_pn_err (up_status_pn_err_s[1]), - .up_adc_pn_oos (up_status_pn_oos_s[1]), - .up_adc_or (up_status_or_s[1]), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[1]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[1]), - .up_rack (up_rack_s[1])); - - // common processor control - - up_adc_common #(.ID(ID)) i_up_adc_common ( - .mmcm_rst (), - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_r1_mode (), - .adc_ddr_edgesel (), - .adc_pin_mode (), - .adc_status (adc_status_s), - .adc_sync_status (1'd0), - .adc_status_ovf (adc_dovf), - .adc_clk_ratio (32'd1), - .adc_start_code (), - .adc_sref_sync (), - .adc_sync (), - .up_adc_ce (), - .up_status_pn_err (up_status_pn_err), - .up_status_pn_oos (up_status_pn_oos), - .up_status_or (up_status_or), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (32'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), - .up_usr_chanmax_out (), - .up_usr_chanmax_in (8'd1), - .up_adc_gpio_in (32'd0), - .up_adc_gpio_out (), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[2]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[2]), - .up_rack (up_rack_s[2])); - - // up bus interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata), - .up_rack (up_rack)); + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata) + ); endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9250/axi_ad9250_channel.v b/library/axi_ad9250/axi_ad9250_channel.v deleted file mode 100644 index e1d2270ef..000000000 --- a/library/axi_ad9250/axi_ad9250_channel.v +++ /dev/null @@ -1,155 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// ADC channel- - -`timescale 1ns/100ps - -module axi_ad9250_channel #( - - parameter CHANNEL_ID = 0) ( - - // adc interface - - input adc_clk, - input adc_rst, - input [27:0] adc_data, - input adc_or, - - // channel interface - - output [31:0] adc_dfmt_data, - output adc_enable, - output up_adc_pn_err, - output up_adc_pn_oos, - output up_adc_or, - - // processor interface - - input up_rstn, - input up_clk, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output up_wack, - input up_rreq, - input [13:0] up_raddr, - output [31:0] up_rdata, - output up_rack); - - - // internal signals - - wire adc_pn_oos_s; - wire adc_pn_err_s; - wire [ 3:0] adc_pnseq_sel_s; - wire adc_dfmt_enable_s; - wire adc_dfmt_type_s; - wire adc_dfmt_se_s; - - // instantiations - - axi_ad9250_pnmon i_pnmon ( - .adc_clk (adc_clk), - .adc_data (adc_data), - .adc_pn_oos (adc_pn_oos_s), - .adc_pn_err (adc_pn_err_s), - .adc_pnseq_sel (adc_pnseq_sel_s)); - - genvar n; - generate - for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1 - ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( - .clk (adc_clk), - .valid (1'b1), - .data (adc_data[n*14+13:n*14]), - .valid_out (), - .data_out (adc_dfmt_data[n*16+15:n*16]), - .dfmt_enable (adc_dfmt_enable_s), - .dfmt_type (adc_dfmt_type_s), - .dfmt_se (adc_dfmt_se_s)); - end - endgenerate - - up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_enable (adc_enable), - .adc_iqcor_enb (), - .adc_dcfilt_enb (), - .adc_dfmt_se (adc_dfmt_se_s), - .adc_dfmt_type (adc_dfmt_type_s), - .adc_dfmt_enable (adc_dfmt_enable_s), - .adc_dcfilt_offset (), - .adc_dcfilt_coeff (), - .adc_iqcor_coeff_1 (), - .adc_iqcor_coeff_2 (), - .adc_pnseq_sel (adc_pnseq_sel_s), - .adc_data_sel (), - .adc_pn_err (adc_pn_err_s), - .adc_pn_oos (adc_pn_oos_s), - .adc_or (adc_or), - .up_adc_pn_err (up_adc_pn_err), - .up_adc_pn_oos (up_adc_pn_oos), - .up_adc_or (up_adc_or), - .up_usr_datatype_be (), - .up_usr_datatype_signed (), - .up_usr_datatype_shift (), - .up_usr_datatype_total_bits (), - .up_usr_datatype_bits (), - .up_usr_decimation_m (), - .up_usr_decimation_n (), - .adc_usr_datatype_be (1'b0), - .adc_usr_datatype_signed (1'b1), - .adc_usr_datatype_shift (8'd0), - .adc_usr_datatype_total_bits (8'd16), - .adc_usr_datatype_bits (8'd16), - .adc_usr_decimation_m (16'd1), - .adc_usr_decimation_n (16'd1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index a5a9b9e6c..e83a0405f 100644 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -24,9 +24,14 @@ add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v -add_fileset_file axi_ad9250_pnmon.v VERILOG PATH axi_ad9250_pnmon.v -add_fileset_file axi_ad9250_if.v VERILOG PATH axi_ad9250_if.v -add_fileset_file axi_ad9250_channel.v VERILOG PATH axi_ad9250_channel.v + +add_fileset_file ad_ip_jesd204_adc_pnmon.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v +add_fileset_file ad_ip_jesd204_adc_channel.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v +add_fileset_file ad_ip_jesd204_adc_core.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v +add_fileset_file ad_ip_jesd204_adc_deframer.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v +add_fileset_file ad_ip_jesd204_adc_regmap.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +add_fileset_file ad_ip_jesd204_adc.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v + add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc @@ -61,7 +66,6 @@ set_interface_property if_rx_data dataBitsPerSymbol 64 # dma interface ad_alt_intf clock adc_clk output 1 -ad_alt_intf reset adc_rst output 1 if_adc_clk add_interface adc_ch_0 conduit end add_interface_port adc_ch_0 adc_enable_a enable Output 1 diff --git a/library/axi_ad9250/axi_ad9250_if.v b/library/axi_ad9250/axi_ad9250_if.v deleted file mode 100644 index 00cba61bc..000000000 --- a/library/axi_ad9250/axi_ad9250_if.v +++ /dev/null @@ -1,115 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9250_if ( - - // jesd interface - // rx_clk is (line-rate/40) - - input rx_clk, - input [ 3:0] rx_sof, - input [63:0] rx_data, - - // adc data output - - output adc_clk, - input adc_rst, - output [27:0] adc_data_a, - output [27:0] adc_data_b, - output adc_or_a, - output adc_or_b, - output reg adc_status); - - - // internal registers - - // internal signals - - wire [15:0] adc_data_a_s1_s; - wire [15:0] adc_data_a_s0_s; - wire [15:0] adc_data_b_s1_s; - wire [15:0] adc_data_b_s0_s; - wire [63:0] rx_data_s; - - // adc clock is the reference clock - - assign adc_clk = rx_clk; - assign adc_or_a = 1'b0; - assign adc_or_b = 1'b0; - - // adc channels - - assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; - assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; - - // data multiplex - - assign adc_data_a_s1_s = {rx_data_s[25:24], rx_data_s[23:16], rx_data_s[31:26]}; - assign adc_data_a_s0_s = {rx_data_s[ 9: 8], rx_data_s[ 7: 0], rx_data_s[15:10]}; - assign adc_data_b_s1_s = {rx_data_s[57:56], rx_data_s[55:48], rx_data_s[63:58]}; - assign adc_data_b_s0_s = {rx_data_s[41:40], rx_data_s[39:32], rx_data_s[47:42]}; - - // status - - always @(posedge rx_clk) begin - if (adc_rst == 1'b1) begin - adc_status <= 1'b0; - end else begin - adc_status <= 1'b1; - end - end - - // frame-alignment - - genvar n; - - generate - for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if - ad_xcvr_rx_if i_xcvr_if ( - .rx_clk (rx_clk), - .rx_ip_sof (rx_sof), - .rx_ip_data (rx_data[((n*32)+31):(n*32)]), - .rx_sof (), - .rx_data (rx_data_s[((n*32)+31):(n*32)])); - end - endgenerate - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl index fc6c7885d..0267c6a5a 100644 --- a/library/axi_ad9250/axi_ad9250_ip.tcl +++ b/library/axi_ad9250/axi_ad9250_ip.tcl @@ -5,27 +5,14 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9250 adi_ip_files axi_ad9250 [list \ - "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/ad_pnmon.v" \ - "$ad_hdl_dir/library/common/ad_datafmt.v" \ - "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/up_clock_mon.v" \ - "$ad_hdl_dir/library/common/up_adc_common.v" \ - "$ad_hdl_dir/library/common/up_adc_channel.v" \ - "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ - "axi_ad9250_pnmon.v" \ - "axi_ad9250_channel.v" \ - "axi_ad9250_if.v" \ "axi_ad9250.v" ] adi_ip_properties axi_ad9250 +adi_ip_add_core_dependencies { \ + analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ +} + set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] @@ -33,4 +20,3 @@ ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_co ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::save_core [ipx::current_core] - diff --git a/library/axi_ad9250/axi_ad9250_pnmon.v b/library/axi_ad9250/axi_ad9250_pnmon.v deleted file mode 100644 index 59e134ea7..000000000 --- a/library/axi_ad9250/axi_ad9250_pnmon.v +++ /dev/null @@ -1,167 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// PN monitors - -`timescale 1ns/100ps - -module axi_ad9250_pnmon ( - - // adc interface - - input adc_clk, - input [27:0] adc_data, - - // pn out of sync and error - - output adc_pn_oos, - output adc_pn_err, - - // processor interface - - input [ 3:0] adc_pnseq_sel); - - // internal registers - - reg [27:0] adc_pn_data_in = 'd0; - reg [27:0] adc_pn_data_pn = 'd0; - - // internal signals - - wire [27:0] adc_pn_data_pn_s; - - // PN23 function - - function [27:0] pn23; - input [27:0] din; - reg [27:0] dout; - begin - dout[27] = din[22] ^ din[17]; - dout[26] = din[21] ^ din[16]; - dout[25] = din[20] ^ din[15]; - dout[24] = din[19] ^ din[14]; - dout[23] = din[18] ^ din[13]; - dout[22] = din[17] ^ din[12]; - dout[21] = din[16] ^ din[11]; - dout[20] = din[15] ^ din[10]; - dout[19] = din[14] ^ din[ 9]; - dout[18] = din[13] ^ din[ 8]; - dout[17] = din[12] ^ din[ 7]; - dout[16] = din[11] ^ din[ 6]; - dout[15] = din[10] ^ din[ 5]; - dout[14] = din[ 9] ^ din[ 4]; - dout[13] = din[ 8] ^ din[ 3]; - dout[12] = din[ 7] ^ din[ 2]; - dout[11] = din[ 6] ^ din[ 1]; - dout[10] = din[ 5] ^ din[ 0]; - dout[ 9] = din[ 4] ^ din[22] ^ din[17]; - dout[ 8] = din[ 3] ^ din[21] ^ din[16]; - dout[ 7] = din[ 2] ^ din[20] ^ din[15]; - dout[ 6] = din[ 1] ^ din[19] ^ din[14]; - dout[ 5] = din[ 0] ^ din[18] ^ din[13]; - dout[ 4] = din[22] ^ din[12]; - dout[ 3] = din[21] ^ din[11]; - dout[ 2] = din[20] ^ din[10]; - dout[ 1] = din[19] ^ din[ 9]; - dout[ 0] = din[18] ^ din[ 8]; - pn23 = dout; - end - endfunction - - // PN9 function - - function [27:0] pn9; - input [27:0] din; - reg [27:0] dout; - begin - dout[27] = din[ 8] ^ din[ 4]; - dout[26] = din[ 7] ^ din[ 3]; - dout[25] = din[ 6] ^ din[ 2]; - dout[24] = din[ 5] ^ din[ 1]; - dout[23] = din[ 4] ^ din[ 0]; - dout[22] = din[ 3] ^ din[ 8] ^ din[ 4]; - dout[21] = din[ 2] ^ din[ 7] ^ din[ 3]; - dout[20] = din[ 1] ^ din[ 6] ^ din[ 2]; - dout[19] = din[ 0] ^ din[ 5] ^ din[ 1]; - dout[18] = din[ 8] ^ din[ 0]; - dout[17] = din[ 7] ^ din[ 8] ^ din[ 4]; - dout[16] = din[ 6] ^ din[ 7] ^ din[ 3]; - dout[15] = din[ 5] ^ din[ 6] ^ din[ 2]; - dout[14] = din[ 4] ^ din[ 5] ^ din[ 1]; - dout[13] = din[ 3] ^ din[ 4] ^ din[ 0]; - dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; - dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; - dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; - dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; - dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; - dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; - dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; - dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; - dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; - dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; - dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; - dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - pn9 = dout; - end - endfunction - - // pn sequence select - - assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; - - always @(posedge adc_clk) begin - adc_pn_data_in <= {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]}; - if (adc_pnseq_sel == 4'd0) begin - adc_pn_data_pn <= pn9(adc_pn_data_pn_s); - end else begin - adc_pn_data_pn <= pn23(adc_pn_data_pn_s); - end - end - - // pn oos & pn err - - ad_pnmon #(.DATA_WIDTH(28)) i_pnmon ( - .adc_clk (adc_clk), - .adc_valid_in (1'b1), - .adc_data_in (adc_pn_data_in), - .adc_data_pn (adc_pn_data_pn), - .adc_pn_oos (adc_pn_oos), - .adc_pn_err (adc_pn_err)); - -endmodule - -// *************************************************************************** -// *************************************************************************** -