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usrpe31x: Use new pack/unpack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-10-04 13:08:06 +02:00 committed by Adrian Costina
parent aed8478d10
commit 76f6428bfc
2 changed files with 43 additions and 44 deletions
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4
projects/usrpe31x/Makefile
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@ -10,8 +10,8 @@ M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl
LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += util_cpack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_upack
include ../scripts/project-xilinx.mk

83
projects/usrpe31x/system_bd.tcl
View File

@ -153,16 +153,17 @@ ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 23
ad_ip_instance axi_dmac axi_ad9361_dac_dma
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_upack util_ad9361_dac_upack
ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4
ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16
ad_ip_instance util_upack2 util_ad9361_dac_upack { \
NUM_OF_CHANNELS 4 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance axi_dmac axi_ad9361_adc_dma
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2
@ -174,9 +175,10 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_instance util_cpack util_ad9361_adc_pack
ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4
ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16
ad_ip_instance util_cpack2 util_ad9361_adc_pack { \
NUM_OF_CHANNELS 4 \
SAMPLE_DATA_WIDTH 16 \
}
# connections
@ -194,42 +196,39 @@ ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect sys_200m_clk axi_ad9361/delay_clk
ad_connect axi_ad9361/l_clk axi_ad9361/clk
ad_connect axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk
ad_connect axi_ad9361/rst util_ad9361_adc_pack/adc_rst
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1
ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_pack/adc_enable_2
ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_pack/adc_valid_2
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_pack/adc_data_2
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_pack/adc_enable_3
ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_pack/adc_valid_3
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_pack/adc_data_3
ad_connect axi_ad9361/l_clk util_ad9361_adc_pack/clk
ad_connect axi_ad9361/rst util_ad9361_adc_pack/reset
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/fifo_wr_en
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/enable_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/fifo_wr_data_0
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/enable_1
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/fifo_wr_data_1
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_pack/enable_2
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_pack/fifo_wr_data_2
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_pack/enable_3
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_pack/fifo_wr_data_3
ad_connect axi_ad9361/adc_dovf util_ad9361_adc_pack/fifo_wr_overflow
ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf
ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0
ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0
ad_connect axi_ad9361/dac_data_i0 util_ad9361_dac_upack/dac_data_0
ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1
ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1
ad_connect axi_ad9361/dac_data_q0 util_ad9361_dac_upack/dac_data_1
ad_connect axi_ad9361/dac_enable_i1 util_ad9361_dac_upack/dac_enable_2
ad_connect axi_ad9361/dac_valid_i1 util_ad9361_dac_upack/dac_valid_2
ad_connect axi_ad9361/dac_data_i1 util_ad9361_dac_upack/dac_data_2
ad_connect axi_ad9361/dac_enable_q1 util_ad9361_dac_upack/dac_enable_3
ad_connect axi_ad9361/dac_valid_q1 util_ad9361_dac_upack/dac_valid_3
ad_connect axi_ad9361/dac_data_q1 util_ad9361_dac_upack/dac_data_3
ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr
ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/clk
ad_connect axi_ad9361/rst util_ad9361_dac_upack/reset
ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/fifo_rd_en
ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/enable_0
ad_connect axi_ad9361/dac_data_i0 util_ad9361_dac_upack/fifo_rd_data_0
ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/enable_1
ad_connect axi_ad9361/dac_data_q0 util_ad9361_dac_upack/fifo_rd_data_1
ad_connect axi_ad9361/dac_enable_i1 util_ad9361_dac_upack/enable_2
ad_connect axi_ad9361/dac_data_i1 util_ad9361_dac_upack/fifo_rd_data_2
ad_connect axi_ad9361/dac_enable_q1 util_ad9361_dac_upack/enable_3
ad_connect axi_ad9361/dac_data_q1 util_ad9361_dac_upack/fifo_rd_data_3
ad_connect axi_ad9361/dac_dunf util_ad9361_dac_upack/fifo_rd_underflow
ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk
ad_connect util_ad9361_dac_upack/s_axis axi_ad9361_dac_dma/m_axis
# interconnects