zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_pwm_gen: Add config in soft reset option

main
AndreiGrozav 2021-07-28 11:17:09 +03:00 committed by sarpadi
parent 591a23156b
commit 76cd5581bc
3 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/axi_pwm_gen/axi_pwm_gen.v
View File

@ -192,7 +192,7 @@ module axi_pwm_gen #(
// offset counter // offset counter
always @(posedge clk) begin always @(posedge clk) begin
if (offset_alignment) begin if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0) begin
offset_cnt <= 32'd0; offset_cnt <= 32'd0;
end else begin end else begin
offset_cnt <= offset_cnt + 1'b1; offset_cnt <= offset_cnt + 1'b1;

16
library/axi_pwm_gen/axi_pwm_gen_1.v
View File

@ -55,10 +55,10 @@ module axi_pwm_gen_1 #(
// internal registers // internal registers
reg [31:0] pulse_period_cnt = 32'h0; reg [31:0] pulse_period_cnt = 32'h0;
reg [31:0] pulse_period_read = 32'b0; reg [31:0] pulse_period_read = PULSE_PERIOD;
reg [31:0] pulse_width_read = 32'b0; reg [31:0] pulse_width_read = PULSE_WIDTH;
reg [31:0] pulse_period_d = 32'b0; reg [31:0] pulse_period_d = PULSE_PERIOD;
reg [31:0] pulse_width_d = 32'b0; reg [31:0] pulse_width_d = PULSE_WIDTH;
reg phase_align_armed = 1'b1; reg phase_align_armed = 1'b1;
// internal wires // internal wires
@ -76,10 +76,10 @@ module axi_pwm_gen_1 #(
always @(posedge clk) begin always @(posedge clk) begin
if (rstn == 1'b0) begin if (rstn == 1'b0) begin
pulse_period_d <= PULSE_PERIOD; pulse_period_d <= pulse_period;
pulse_width_d <= PULSE_WIDTH; pulse_width_d <= pulse_width;
pulse_period_read <= PULSE_PERIOD; pulse_period_read <= pulse_period;
pulse_width_read <= PULSE_WIDTH; pulse_width_read <= pulse_width;
end else begin end else begin
// load the input period/width values // load the input period/width values
if (load_config) begin if (load_config) begin

2
library/axi_pwm_gen/axi_pwm_gen_regmap.v
View File

@ -98,7 +98,7 @@ module axi_pwm_gen_regmap #(
reg [31:0] up_pwm_offset_2 = PULSE_2_OFFSET; reg [31:0] up_pwm_offset_2 = PULSE_2_OFFSET;
reg [31:0] up_pwm_offset_3 = PULSE_3_OFFSET; reg [31:0] up_pwm_offset_3 = PULSE_3_OFFSET;
reg up_load_config = 1'b0; reg up_load_config = 1'b0;
reg up_reset; reg up_reset = 1'b1;
always @(posedge up_clk) begin always @(posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin