board-tcl: xcvr qpll/cpll changes
parent
2ea997c3d5
commit
750b23621b
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@ -122,7 +122,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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set index $xcvr_tx_index
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}
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create_bd_port -dir I ${txrx}_ref_clk_${index}
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create_bd_port -dir I ${txrx}_sysref_${index}
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create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index}
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create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen
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@ -144,14 +143,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
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if {(($m%4) == 0) && ($qpll_enable == 1)} {
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ad_connect ${u_xcvr}/qpll_ref_clk_${m} ${txrx}_ref_clk_${index}
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}
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if {$qpll_enable == 0} {
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ad_connect ${u_xcvr}/cpll_ref_clk_${m} ${txrx}_ref_clk_${index}
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}
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create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p
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create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n
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ad_connect ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p
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