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board-tcl: xcvr qpll/cpll changes

main
Rejeesh Kutty 2016-11-22 12:53:02 -05:00
parent 2ea997c3d5
commit 750b23621b
1 changed files with 0 additions and 9 deletions
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9
projects/scripts/adi_board.tcl
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@ -122,7 +122,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
set index $xcvr_tx_index set index $xcvr_tx_index
} }
create_bd_port -dir I ${txrx}_ref_clk_${index}
create_bd_port -dir I ${txrx}_sysref_${index} create_bd_port -dir I ${txrx}_sysref_${index}
create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index} create_bd_port -dir ${ctrl_dir} ${txrx}_sync_${index}
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ${a_jesd}_rstgen
@ -144,14 +143,6 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx} ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m} ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
if {(($m%4) == 0) && ($qpll_enable == 1)} {
ad_connect ${u_xcvr}/qpll_ref_clk_${m} ${txrx}_ref_clk_${index}
}
if {$qpll_enable == 0} {
ad_connect ${u_xcvr}/cpll_ref_clk_${m} ${txrx}_ref_clk_${index}
}
create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p create_bd_port -dir ${data_dir} ${txrx}_data_${m}_p
create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n create_bd_port -dir ${data_dir} ${txrx}_data_${m}_n
ad_connect ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p ad_connect ${u_xcvr}/${txrx}_${m}_p ${txrx}_data_${m}_p