library/common- added dac clock select
parent
271029768c
commit
74bc498a6d
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@ -49,6 +49,7 @@ module up_dac_common (
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dac_rst,
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dac_sync,
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dac_frame,
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dac_clksel,
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dac_par_type,
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dac_par_enb,
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dac_r1_mode,
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@ -105,6 +106,7 @@ module up_dac_common (
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output dac_rst;
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output dac_sync;
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output dac_frame;
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output dac_clksel;
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output dac_par_type;
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output dac_par_enb;
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output dac_r1_mode;
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@ -160,6 +162,7 @@ module up_dac_common (
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reg up_dac_datafmt = 'd0;
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reg [ 7:0] up_dac_datarate = 'd0;
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reg up_dac_frame = 'd0;
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reg up_dac_clksel = 'd0;
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reg up_drp_sel = 'd0;
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reg up_drp_wr = 'd0;
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reg up_drp_status = 'd0;
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@ -215,6 +218,7 @@ module up_dac_common (
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up_dac_datafmt <= 'd0;
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up_dac_datarate <= 'd0;
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up_dac_frame <= 'd0;
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up_dac_clksel <= 'd0;
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up_drp_sel <= 'd0;
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up_drp_wr <= 'd0;
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up_drp_status <= 'd0;
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@ -260,6 +264,9 @@ module up_dac_common (
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_dac_frame <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin
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up_dac_clksel <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
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up_drp_sel <= 1'b1;
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up_drp_wr <= ~up_wdata[28];
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@ -321,6 +328,7 @@ module up_dac_common (
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8'h15: up_rdata <= up_dac_clk_count_s;
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8'h16: up_rdata <= dac_clk_ratio;
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8'h17: up_rdata <= {31'd0, up_status_s};
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8'h18: up_rdata <= {31'd0, up_dac_clksel};
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8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
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8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
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8'h22: up_rdata <= {30'd0, up_status_ovf, up_status_unf};
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@ -342,10 +350,11 @@ module up_dac_common (
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// dac control & status
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up_xfer_cntrl #(.DATA_WIDTH(14)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_dac_sync,
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up_dac_clksel,
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up_dac_frame,
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up_dac_par_type,
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up_dac_par_enb,
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@ -356,6 +365,7 @@ module up_dac_common (
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.d_rst (dac_rst),
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.d_clk (dac_clk),
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.d_data_cntrl ({ dac_sync_s,
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dac_clksel,
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dac_frame_s,
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dac_par_type,
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dac_par_enb,
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