adrv9361z7035:ccusb: Delete deprecated project
Istvan Csomortani
István Csomortáni
parent
62c7ecbbff
commit
748b4598fc
|
|
@ -1,26 +0,0 @@
|
||||||
####################################################################################
|
|
||||||
## Copyright 2018(c) Analog Devices, Inc.
|
|
||||||
## Auto-generated, do not modify!
|
|
||||||
####################################################################################
|
|
||||||
|
|
||||||
PROJECT_NAME := adrv9361z7035_ccusb_lvds
|
|
||||||
|
|
||||||
M_DEPS += ../common/ccusb_constr.xdc
|
|
||||||
M_DEPS += ../common/ccusb_bd.tcl
|
|
||||||
M_DEPS += ../common/adrv9361z7035_constr_lvds.xdc
|
|
||||||
M_DEPS += ../common/adrv9361z7035_constr.xdc
|
|
||||||
M_DEPS += ../common/adrv9361z7035_bd.tcl
|
|
||||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
|
||||||
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl
|
|
||||||
|
|
||||||
LIB_DEPS += axi_ad9361
|
|
||||||
LIB_DEPS += axi_dmac
|
|
||||||
LIB_DEPS += axi_usb_fx3
|
|
||||||
LIB_DEPS += util_clkdiv
|
|
||||||
LIB_DEPS += util_cpack
|
|
||||||
LIB_DEPS += util_rfifo
|
|
||||||
LIB_DEPS += util_tdd_sync
|
|
||||||
LIB_DEPS += util_upack
|
|
||||||
LIB_DEPS += util_wfifo
|
|
||||||
|
|
||||||
include ../../scripts/project-xilinx.mk
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
|
|
||||||
source ../common/adrv9361z7035_bd.tcl
|
|
||||||
source ../common/ccusb_bd.tcl
|
|
||||||
|
|
||||||
cfg_ad9361_interface LVDS
|
|
||||||
|
|
||||||
ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 29
|
|
||||||
|
|
||||||
|
|
@ -1,17 +0,0 @@
|
||||||
|
|
||||||
source ../../scripts/adi_env.tcl
|
|
||||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
|
||||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
|
||||||
|
|
||||||
set p_device "xc7z035ifbg676-2L"
|
|
||||||
adi_project_xilinx adrv9361z7035_ccusb_lvds
|
|
||||||
adi_project_files adrv9361z7035_ccusb_lvds [list \
|
|
||||||
"system_top.v" \
|
|
||||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
|
||||||
"../common/adrv9361z7035_constr.xdc" \
|
|
||||||
"../common/adrv9361z7035_constr_lvds.xdc" \
|
|
||||||
"../common/ccusb_constr.xdc" ]
|
|
||||||
|
|
||||||
adi_project_run adrv9361z7035_ccusb_lvds
|
|
||||||
source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
|
|
||||||
|
|
||||||
|
|
@ -1,239 +0,0 @@
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
|
||||||
//
|
|
||||||
// In this HDL repository, there are many different and unique modules, consisting
|
|
||||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
|
||||||
// developed independently, and may be accompanied by separate and unique license
|
|
||||||
// terms.
|
|
||||||
//
|
|
||||||
// The user should read each of these license terms, and understand the
|
|
||||||
// freedoms and responsibilities that he or she has by using this source/core.
|
|
||||||
//
|
|
||||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
|
||||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
|
||||||
// A PARTICULAR PURPOSE.
|
|
||||||
//
|
|
||||||
// Redistribution and use of source or resulting binaries, with or without modification
|
|
||||||
// of this file, are permitted under one of the following two license terms:
|
|
||||||
//
|
|
||||||
// 1. The GNU General Public License version 2 as published by the
|
|
||||||
// Free Software Foundation, which can be found in the top level directory
|
|
||||||
// of this repository (LICENSE_GPL2), and also online at:
|
|
||||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
|
||||||
//
|
|
||||||
// OR
|
|
||||||
//
|
|
||||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
|
||||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
|
||||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
|
||||||
// This will allow to generate bit files and not release the source code,
|
|
||||||
// as long as it attaches to an ADI device.
|
|
||||||
//
|
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
|
|
||||||
`timescale 1ns/100ps
|
|
||||||
|
|
||||||
module system_top (
|
|
||||||
|
|
||||||
inout [14:0] ddr_addr,
|
|
||||||
inout [ 2:0] ddr_ba,
|
|
||||||
inout ddr_cas_n,
|
|
||||||
inout ddr_ck_n,
|
|
||||||
inout ddr_ck_p,
|
|
||||||
inout ddr_cke,
|
|
||||||
inout ddr_cs_n,
|
|
||||||
inout [ 3:0] ddr_dm,
|
|
||||||
inout [31:0] ddr_dq,
|
|
||||||
inout [ 3:0] ddr_dqs_n,
|
|
||||||
inout [ 3:0] ddr_dqs_p,
|
|
||||||
inout ddr_odt,
|
|
||||||
inout ddr_ras_n,
|
|
||||||
inout ddr_reset_n,
|
|
||||||
inout ddr_we_n,
|
|
||||||
|
|
||||||
inout fixed_io_ddr_vrn,
|
|
||||||
inout fixed_io_ddr_vrp,
|
|
||||||
inout [53:0] fixed_io_mio,
|
|
||||||
inout fixed_io_ps_clk,
|
|
||||||
inout fixed_io_ps_porb,
|
|
||||||
inout fixed_io_ps_srstb,
|
|
||||||
|
|
||||||
inout iic_scl,
|
|
||||||
inout iic_sda,
|
|
||||||
|
|
||||||
input rx_clk_in_p,
|
|
||||||
input rx_clk_in_n,
|
|
||||||
input rx_frame_in_p,
|
|
||||||
input rx_frame_in_n,
|
|
||||||
input [ 5:0] rx_data_in_p,
|
|
||||||
input [ 5:0] rx_data_in_n,
|
|
||||||
output tx_clk_out_p,
|
|
||||||
output tx_clk_out_n,
|
|
||||||
output tx_frame_out_p,
|
|
||||||
output tx_frame_out_n,
|
|
||||||
output [ 5:0] tx_data_out_p,
|
|
||||||
output [ 5:0] tx_data_out_n,
|
|
||||||
|
|
||||||
output enable,
|
|
||||||
output txnrx,
|
|
||||||
input clkout_in,
|
|
||||||
|
|
||||||
inout gpio_clksel,
|
|
||||||
inout gpio_resetb,
|
|
||||||
inout gpio_sync,
|
|
||||||
inout gpio_en_agc,
|
|
||||||
inout [ 3:0] gpio_ctl,
|
|
||||||
inout [ 7:0] gpio_status,
|
|
||||||
|
|
||||||
input usb_fx3_uart_tx,
|
|
||||||
output usb_fx3_uart_rx,
|
|
||||||
|
|
||||||
input [ 7:0] fifo_rdy,
|
|
||||||
|
|
||||||
inout [31:0] data,
|
|
||||||
output [ 4:0] addr,
|
|
||||||
output pclk,
|
|
||||||
output slcs_n,
|
|
||||||
output slrd_n,
|
|
||||||
output sloe_n,
|
|
||||||
output slwr_n,
|
|
||||||
output pktend_n,
|
|
||||||
output epswitch_n,
|
|
||||||
|
|
||||||
input flag_a,
|
|
||||||
input flag_b,
|
|
||||||
|
|
||||||
output reset_n,
|
|
||||||
|
|
||||||
output [ 2:0] pmode,
|
|
||||||
|
|
||||||
output spi_csn,
|
|
||||||
output spi_clk,
|
|
||||||
output spi_mosi,
|
|
||||||
input spi_miso);
|
|
||||||
|
|
||||||
// internal signals
|
|
||||||
|
|
||||||
wire [63:0] gpio_i;
|
|
||||||
wire [63:0] gpio_o;
|
|
||||||
wire [63:0] gpio_t;
|
|
||||||
|
|
||||||
// assignments
|
|
||||||
|
|
||||||
assign pmode = 3'b111;
|
|
||||||
assign addr[4:2] = 3'b000;
|
|
||||||
|
|
||||||
assign epswitch_n = 1'b1;
|
|
||||||
assign reset_n = 1'b1;
|
|
||||||
|
|
||||||
// instantiations
|
|
||||||
|
|
||||||
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
|
|
||||||
.dio_t ({gpio_t[51], gpio_t[46:32]}),
|
|
||||||
.dio_i ({gpio_o[51], gpio_o[46:32]}),
|
|
||||||
.dio_o ({gpio_i[51], gpio_i[46:32]}),
|
|
||||||
.dio_p ({ gpio_clksel, // 51:51
|
|
||||||
gpio_resetb, // 46:46
|
|
||||||
gpio_sync, // 45:45
|
|
||||||
gpio_en_agc, // 44:44
|
|
||||||
gpio_ctl, // 43:40
|
|
||||||
gpio_status})); // 39:32
|
|
||||||
|
|
||||||
system_wrapper i_system_wrapper (
|
|
||||||
.ddr_addr (ddr_addr),
|
|
||||||
.ddr_ba (ddr_ba),
|
|
||||||
.ddr_cas_n (ddr_cas_n),
|
|
||||||
.ddr_ck_n (ddr_ck_n),
|
|
||||||
.ddr_ck_p (ddr_ck_p),
|
|
||||||
.ddr_cke (ddr_cke),
|
|
||||||
.ddr_cs_n (ddr_cs_n),
|
|
||||||
.ddr_dm (ddr_dm),
|
|
||||||
.ddr_dq (ddr_dq),
|
|
||||||
.ddr_dqs_n (ddr_dqs_n),
|
|
||||||
.ddr_dqs_p (ddr_dqs_p),
|
|
||||||
.ddr_odt (ddr_odt),
|
|
||||||
.ddr_ras_n (ddr_ras_n),
|
|
||||||
.ddr_reset_n (ddr_reset_n),
|
|
||||||
.ddr_we_n (ddr_we_n),
|
|
||||||
.enable (enable),
|
|
||||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
||||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
||||||
.fixed_io_mio (fixed_io_mio),
|
|
||||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
||||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
||||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
||||||
.gpio_i (gpio_i),
|
|
||||||
.gpio_o (gpio_o),
|
|
||||||
.gpio_t (gpio_t),
|
|
||||||
.iic_main_scl_io (iic_scl),
|
|
||||||
.iic_main_sda_io (iic_sda),
|
|
||||||
.otg_vbusoc (1'b0),
|
|
||||||
.ps_intr_00 (1'b0),
|
|
||||||
.ps_intr_01 (1'b0),
|
|
||||||
.ps_intr_02 (1'b0),
|
|
||||||
.ps_intr_03 (1'b0),
|
|
||||||
.ps_intr_04 (1'b0),
|
|
||||||
.ps_intr_05 (1'b0),
|
|
||||||
.ps_intr_06 (1'b0),
|
|
||||||
.ps_intr_07 (1'b0),
|
|
||||||
.ps_intr_08 (1'b0),
|
|
||||||
.ps_intr_09 (1'b0),
|
|
||||||
.ps_intr_15 (1'b0),
|
|
||||||
.rx_clk_in_n (rx_clk_in_n),
|
|
||||||
.rx_clk_in_p (rx_clk_in_p),
|
|
||||||
.rx_data_in_n (rx_data_in_n),
|
|
||||||
.rx_data_in_p (rx_data_in_p),
|
|
||||||
.rx_frame_in_n (rx_frame_in_n),
|
|
||||||
.rx_frame_in_p (rx_frame_in_p),
|
|
||||||
.spi0_clk_i (1'b0),
|
|
||||||
.spi0_clk_o (spi_clk),
|
|
||||||
.spi0_csn_0_o (spi_csn),
|
|
||||||
.spi0_csn_1_o (),
|
|
||||||
.spi0_csn_2_o (),
|
|
||||||
.spi0_csn_i (1'b1),
|
|
||||||
.spi0_sdi_i (spi_miso),
|
|
||||||
.spi0_sdo_i (1'b0),
|
|
||||||
.spi0_sdo_o (spi_mosi),
|
|
||||||
.spi1_clk_i (1'b0),
|
|
||||||
.spi1_clk_o (),
|
|
||||||
.spi1_csn_0_o (),
|
|
||||||
.spi1_csn_1_o (),
|
|
||||||
.spi1_csn_2_o (),
|
|
||||||
.spi1_csn_i (1'b1),
|
|
||||||
.spi1_sdi_i (1'b0),
|
|
||||||
.spi1_sdo_i (1'b0),
|
|
||||||
.spi1_sdo_o (),
|
|
||||||
.tdd_sync_i (1'b0),
|
|
||||||
.tdd_sync_o (),
|
|
||||||
.tdd_sync_t (),
|
|
||||||
.tx_clk_out_n (tx_clk_out_n),
|
|
||||||
.tx_clk_out_p (tx_clk_out_p),
|
|
||||||
.tx_data_out_n (tx_data_out_n),
|
|
||||||
.tx_data_out_p (tx_data_out_p),
|
|
||||||
.tx_frame_out_n (tx_frame_out_n),
|
|
||||||
.tx_frame_out_p (tx_frame_out_p),
|
|
||||||
.txnrx (txnrx),
|
|
||||||
.up_enable (gpio_o[47]),
|
|
||||||
.up_txnrx (gpio_o[48]),
|
|
||||||
.usb_fx3_uart_tx(usb_fx3_uart_tx),
|
|
||||||
.usb_fx3_uart_rx(usb_fx3_uart_rx),
|
|
||||||
.dma_rdy(),
|
|
||||||
.dma_wmk(),
|
|
||||||
.fifo_rdy(fifo_rdy[3:0]),
|
|
||||||
.pclk(pclk),
|
|
||||||
.data(data),
|
|
||||||
.addr(addr[1:0]),
|
|
||||||
.slcs_n(slcs_n),
|
|
||||||
.slrd_n(slrd_n),
|
|
||||||
.sloe_n(sloe_n),
|
|
||||||
.slwr_n(slwr_n),
|
|
||||||
// .epswitch_n(epswitch_n),
|
|
||||||
.pktend_n(pktend_n)
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ***************************************************************************
|
|
||||||
// ***************************************************************************
|
|
||||||
|
|
@ -1,74 +0,0 @@
|
||||||
|
|
||||||
ad_connect sys_ps7/ENET1_GMII_RX_CLK GND
|
|
||||||
ad_connect sys_ps7/ENET1_GMII_TX_CLK GND
|
|
||||||
|
|
||||||
create_bd_port -dir I usb_fx3_uart_tx
|
|
||||||
create_bd_port -dir O usb_fx3_uart_rx
|
|
||||||
|
|
||||||
create_bd_port -dir I dma_rdy
|
|
||||||
create_bd_port -dir I dma_wmk
|
|
||||||
create_bd_port -dir I -from 3 -to 0 fifo_rdy
|
|
||||||
create_bd_port -dir O pclk
|
|
||||||
create_bd_port -dir IO -from 31 -to 0 data
|
|
||||||
create_bd_port -dir O -from 1 -to 0 addr
|
|
||||||
create_bd_port -dir O slcs_n
|
|
||||||
create_bd_port -dir O slrd_n
|
|
||||||
create_bd_port -dir O sloe_n
|
|
||||||
create_bd_port -dir O slwr_n
|
|
||||||
create_bd_port -dir O pktend_n
|
|
||||||
create_bd_port -dir O epswitch_n
|
|
||||||
|
|
||||||
ad_ip_instance axi_uartlite axi_uart
|
|
||||||
ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200
|
|
||||||
|
|
||||||
ad_ip_instance axi_usb_fx3 axi_usb_fx3
|
|
||||||
|
|
||||||
ad_ip_instance axi_dma axi_usb_fx3_dma
|
|
||||||
ad_ip_parameter axi_usb_fx3_dma CONFIG.c_sg_include_stscntrl_strm 0
|
|
||||||
ad_ip_parameter axi_usb_fx3_dma CONFIG.c_mm2s_burst_size 256
|
|
||||||
ad_ip_parameter axi_usb_fx3_dma CONFIG.c_s2mm_burst_size 256
|
|
||||||
ad_ip_parameter axi_usb_fx3_dma CONFIG.c_sg_length_width 16
|
|
||||||
|
|
||||||
ad_ip_instance axis_data_fifo usb_fx3_rx_axis_fifo
|
|
||||||
|
|
||||||
ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
|
|
||||||
|
|
||||||
ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
|
|
||||||
ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
|
|
||||||
|
|
||||||
ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
|
|
||||||
ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
|
|
||||||
|
|
||||||
ad_connect axi_uart/rx usb_fx3_uart_tx
|
|
||||||
ad_connect axi_uart/tx usb_fx3_uart_rx
|
|
||||||
|
|
||||||
ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
|
|
||||||
ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
|
|
||||||
|
|
||||||
ad_connect axi_usb_fx3/dma_rdy dma_rdy
|
|
||||||
ad_connect axi_usb_fx3/dma_wmk dma_wmk
|
|
||||||
ad_connect axi_usb_fx3/fifo_rdy fifo_rdy
|
|
||||||
ad_connect axi_usb_fx3/pclk pclk
|
|
||||||
ad_connect axi_usb_fx3/data data
|
|
||||||
ad_connect axi_usb_fx3/addr addr
|
|
||||||
ad_connect axi_usb_fx3/slcs_n slcs_n
|
|
||||||
ad_connect axi_usb_fx3/slrd_n slrd_n
|
|
||||||
ad_connect axi_usb_fx3/sloe_n sloe_n
|
|
||||||
ad_connect axi_usb_fx3/slwr_n slwr_n
|
|
||||||
ad_connect axi_usb_fx3/pktend_n pktend_n
|
|
||||||
ad_connect axi_usb_fx3/epswitch_n epswitch_n
|
|
||||||
|
|
||||||
|
|
||||||
ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
|
|
||||||
ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
|
|
||||||
ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
|
|
||||||
ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
|
|
||||||
|
|
||||||
ad_cpu_interconnect 0x50000000 axi_usb_fx3
|
|
||||||
ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
|
|
||||||
ad_cpu_interconnect 0x40600000 axi_uart
|
|
||||||
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
|
|
||||||
ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
|
|
||||||
|
|
@ -1,74 +0,0 @@
|
||||||
# Default constraints have LVCMOS25, overwite it
|
|
||||||
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ;
|
|
||||||
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ;
|
|
||||||
|
|
||||||
# USB_FX3
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports data[30]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports data[31]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports data[24]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports data[27]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports data[26]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports data[21]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports data[18]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports data[19]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports data[23]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports data[20]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports data[2]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports data[14]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports data[13]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports data[9]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports data[12]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports data[8]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports data[7]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports data[3]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports data[0]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports data[4]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports data[5]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports data[28]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports data[29]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports data[25]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports data[22]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports data[16]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports data[17]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports data[15]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports data[11]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports data[10]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports data[6]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports data[1]] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports pclk] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports addr[0]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports addr[1]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports addr[2]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports addr[3]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports addr[4]] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports slcs_n] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports slwr_n] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports sloe_n] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports slrd_n] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS18} [get_ports pktend_n] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[4]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[5]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[6]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[7]] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports flag_a] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS18} [get_ports flag_b] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports pmode[0]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports pmode[1]] ;
|
|
||||||
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmode[2]] ;
|
|
||||||
|
|
||||||
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports reset_n] ;
|
|
||||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports epswitch_n] ;
|
|
||||||
Loading…
Reference in New Issue