axi_dacfifo: Match the ports with util_dacfifo

library/xilinx/axi_dacfifo/axi_dacfifo.v

@@ -44,6 +44,7 @@ module axi_dacfifo (
   // dma interface (AXI Stream)
 
   dma_clk,
+  dma_rst,
   dma_valid,
   dma_data,
   dma_ready,
@@ -123,6 +124,7 @@ module axi_dacfifo (
   // dma interface
 
   input                               dma_clk;
+  input                               dma_rst;
   input                               dma_valid;
   input   [(DMA_DATA_WIDTH-1):0]      dma_data;
   output                              dma_ready;

library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl

@@ -28,6 +28,7 @@ ad_ip_parameter AXI_ADDRESS_LIMIT INTEGER -1
 # interfaces
 
 ad_alt_intf clock dma_clk input 1 clk
+ad_alt_intf reset dma_rst input 1 if_dma_clk
 ad_alt_intf signal dma_valid input 1 valid
 ad_alt_intf signal dma_data input DMA_DATA_WIDTH data
 ad_alt_intf signal dma_ready output 1 ready