spi_engine: Software reset should reset the offload control registers too
parent
19655b8092
commit
746f457ef9
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@ -265,24 +265,34 @@ always @(posedge clk) begin
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up_wack_ff <= 1'b0;
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up_scratch <= 'h00;
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up_sw_reset <= 1'b1;
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up_irq_mask <= 'h00;
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offload0_enable <= 1'b0;
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offload0_mem_reset <= 1'b0;
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end else begin
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up_wack_ff <= up_wreq_s;
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offload0_mem_reset <= 1'b0;
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h02: up_scratch <= up_wdata_s;
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8'h10: up_sw_reset <= up_wdata_s;
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable <= up_wdata_s[0];
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8'h42: offload0_mem_reset <= up_wdata_s[0];
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endcase
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end
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end
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end
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// the software reset should reset all the registers
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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up_irq_mask <= 'h00;
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offload0_enable <= 1'b0;
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offload0_mem_reset <= 1'b0;
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end else begin
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable <= up_wdata_s[0];
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8'h42: offload0_mem_reset <= up_wdata_s[0];
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_rack_ff <= 'd0;
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