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spi_engine: Software reset should reset the offload control registers too

main
Istvan Csomortani 2018-09-14 10:27:36 +01:00 committed by István Csomortáni
parent 19655b8092
commit 746f457ef9
1 changed files with 17 additions and 7 deletions
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24
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -265,24 +265,34 @@ always @(posedge clk) begin
up_wack_ff <= 1'b0; up_wack_ff <= 1'b0;
up_scratch <= 'h00; up_scratch <= 'h00;
up_sw_reset <= 1'b1; up_sw_reset <= 1'b1;
up_irq_mask <= 'h00;
offload0_enable <= 1'b0;
offload0_mem_reset <= 1'b0;
end else begin end else begin
up_wack_ff <= up_wreq_s; up_wack_ff <= up_wreq_s;
offload0_mem_reset <= 1'b0;
if (up_wreq_s) begin if (up_wreq_s) begin
case (up_waddr_s) case (up_waddr_s)
8'h02: up_scratch <= up_wdata_s; 8'h02: up_scratch <= up_wdata_s;
8'h10: up_sw_reset <= up_wdata_s; 8'h10: up_sw_reset <= up_wdata_s;
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable <= up_wdata_s[0];
8'h42: offload0_mem_reset <= up_wdata_s[0];
endcase endcase
end end
end end
end end
// the software reset should reset all the registers
always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin
up_irq_mask <= 'h00;
offload0_enable <= 1'b0;
offload0_mem_reset <= 1'b0;
end else begin
if (up_wreq_s) begin
case (up_waddr_s)
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable <= up_wdata_s[0];
8'h42: offload0_mem_reset <= up_wdata_s[0];
endcase
end
end
end
always @(posedge clk) begin always @(posedge clk) begin
if (rstn == 1'b0) begin if (rstn == 1'b0) begin
up_rack_ff <= 'd0; up_rack_ff <= 'd0;