xilin/axi_adxcvr: Fix clock and reset nets[C

main
Istvan Csomortani 2017-01-19 15:46:16 +02:00
parent 57bd6acd0f
commit 746b97dd96
1 changed files with 2 additions and 2 deletions

View File

@ -661,8 +661,8 @@ module axi_adxcvr (
// channel broadcast
assign up_rstn = axi_aresetn;
assign up_clk = axi_clk;
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign up_cm_sel_0 = up_cm_sel;
assign up_cm_enb_0 = up_cm_enb;