xilin/axi_adxcvr: Fix clock and reset nets[C
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57bd6acd0f
commit
746b97dd96
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@ -661,8 +661,8 @@ module axi_adxcvr (
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// channel broadcast
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assign up_rstn = axi_aresetn;
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assign up_clk = axi_clk;
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assign up_rstn = s_axi_aresetn;
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assign up_clk = s_axi_aclk;
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assign up_cm_sel_0 = up_cm_sel;
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assign up_cm_enb_0 = up_cm_enb;
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