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axi_ad9379: Update for CORDIC algorithm 

Add the new files to the IP list
Propagate DDS parameters to top file
main
AndreiGrozav 2018-02-07 14:50:46 +02:00 committed by AndreiGrozav
parent 2ce10f4504
commit 74609d8fec
4 changed files with 37 additions and 12 deletions
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2
library/axi_adrv9009/axi_adrv9009_hw.tcl
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@ -16,6 +16,8 @@ add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_adrv9009 set_fileset_property quartus_synth TOP_LEVEL axi_adrv9009
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dds_cordic_pipe.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v
add_fileset_file ad_dds_sine_cordic.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine_cordic.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v

2
library/axi_adrv9009/axi_adrv9009_ip.tcl
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@ -12,6 +12,8 @@ adi_ip_files axi_adrv9009 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \

29
library/axi_adrv9009/axi_adrv9009_tx.v
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@ -38,8 +38,11 @@
module axi_adrv9009_tx #( module axi_adrv9009_tx #(
parameter ID = 0, parameter ID = 0,
parameter DISABLE = 0,
parameter DDS_DISABLE = 0, parameter DDS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16) (
// dac interface // dac interface
@ -132,9 +135,11 @@ module axi_adrv9009_tx #(
axi_adrv9009_tx_channel #( axi_adrv9009_tx_channel #(
.CHANNEL_ID (0), .CHANNEL_ID (0),
.Q_OR_I_N (0), .Q_OR_I_N (0),
.DISABLE (0), .DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE), .DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW))
i_tx_channel_0 ( i_tx_channel_0 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -163,9 +168,11 @@ module axi_adrv9009_tx #(
axi_adrv9009_tx_channel #( axi_adrv9009_tx_channel #(
.CHANNEL_ID (1), .CHANNEL_ID (1),
.Q_OR_I_N (1), .Q_OR_I_N (1),
.DISABLE (0), .DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE), .DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW))
i_tx_channel_1 ( i_tx_channel_1 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -194,9 +201,11 @@ module axi_adrv9009_tx #(
axi_adrv9009_tx_channel #( axi_adrv9009_tx_channel #(
.CHANNEL_ID (2), .CHANNEL_ID (2),
.Q_OR_I_N (0), .Q_OR_I_N (0),
.DISABLE (0), .DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE), .DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW))
i_tx_channel_2 ( i_tx_channel_2 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),
@ -225,9 +234,11 @@ module axi_adrv9009_tx #(
axi_adrv9009_tx_channel #( axi_adrv9009_tx_channel #(
.CHANNEL_ID (3), .CHANNEL_ID (3),
.Q_OR_I_N (1), .Q_OR_I_N (1),
.DISABLE (0), .DISABLE (DISABLE),
.DDS_DISABLE (DDS_DISABLE), .DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)) .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW))
i_tx_channel_3 ( i_tx_channel_3 (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),

16
library/axi_adrv9009/axi_adrv9009_tx_channel.v
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@ -41,7 +41,9 @@ module axi_adrv9009_tx_channel #(
parameter Q_OR_I_N = 0, parameter Q_OR_I_N = 0,
parameter DISABLE = 0, parameter DISABLE = 0,
parameter DDS_DISABLE = 0, parameter DDS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0) ( parameter IQCORRECTION_DISABLE = 0,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16) (
// dac interface // dac interface
@ -183,7 +185,11 @@ module axi_adrv9009_tx_channel #(
end else begin end else begin
ad_dds i_dds_0 ( ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_0 (
.clk (dac_clk), .clk (dac_clk),
.dds_format (dac_dds_format), .dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0), .dds_phase_0 (dac_dds_phase_0_0),
@ -192,7 +198,11 @@ module axi_adrv9009_tx_channel #(
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s)); .dds_data (dac_dds_data_0_s));
ad_dds i_dds_1 ( ad_dds #(
.DISABLE (0),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW))
i_dds_1 (
.clk (dac_clk), .clk (dac_clk),
.dds_format (dac_dds_format), .dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0), .dds_phase_0 (dac_dds_phase_1_0),