From 734fdab326873f230b44bd3107f5b7138bf074b4 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 23 Apr 2015 10:23:22 +0300 Subject: [PATCH] axi_ad9234: Added CDC and reset constraints --- library/axi_ad9234/axi_ad9234_constr.xdc | 40 ++++++++++++++++++++++++ library/axi_ad9234/axi_ad9234_ip.tcl | 1 + 2 files changed, 41 insertions(+) diff --git a/library/axi_ad9234/axi_ad9234_constr.xdc b/library/axi_ad9234/axi_ad9234_constr.xdc index fd40910d9..9b39510fb 100644 --- a/library/axi_ad9234/axi_ad9234_constr.xdc +++ b/library/axi_ad9234/axi_ad9234_constr.xdc @@ -1,4 +1,44 @@ +set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set ad9234_clk [get_clocks -of_objects [get_ports rx_clk]] +set_property ASYNC_REG TRUE \ + [get_cells -hier *toggle_m1_reg*] \ + [get_cells -hier *toggle_m2_reg*] \ + [get_cells -hier *state_m1_reg*] \ + [get_cells -hier *state_m2_reg*] +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $ad9234_clk] +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] +set_false_path \ + -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] + +set_false_path \ + -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl index 02153c704..04b7eda12 100644 --- a/library/axi_ad9234/axi_ad9234_ip.tcl +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -23,6 +23,7 @@ adi_ip_files axi_ad9234 [list \ "axi_ad9234_constr.xdc" ] adi_ip_properties axi_ad9234 + adi_ip_constraints axi_ad9234 [list \ "axi_ad9234_constr.xdc" ]