From 7340d8aa16290ee97ff883c65dd96c7dea49ab4d Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 6 Jul 2017 09:52:39 +0100 Subject: [PATCH] axi_dacfifo: DAC side CDC fifo control update The fifo will ask for a new data from the DDR, if the current level is lower than the high threshold. This will prevent overflow. By deleting the lower threshold, we can avoid ocassional underflows, when the DAC rate is closer to the max DDRx rate. --- library/xilinx/axi_dacfifo/axi_dacfifo_dac.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v index 447dd8707..25de4dac6 100644 --- a/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v +++ b/library/xilinx/axi_dacfifo/axi_dacfifo_dac.v @@ -186,7 +186,7 @@ module axi_dacfifo_dac #( axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0]; if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin axi_dready <= 1'b0; - end else if (axi_mem_addr_diff <= AXI_BUF_THRESHOLD_LO) begin + end else begin axi_dready <= 1'b1; end end