diff --git a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl new file mode 100755 index 000000000..46df71e71 --- /dev/null +++ b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl @@ -0,0 +1,292 @@ + +# usdrx1 + +set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i] +set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o] +set spi_clk_i [create_bd_port -dir I spi_clk_i] +set spi_clk_o [create_bd_port -dir O spi_clk_o] +set spi_sdo_i [create_bd_port -dir I spi_sdo_i] +set spi_sdo_o [create_bd_port -dir O spi_sdo_o] +set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + +set rx_ref_clk [create_bd_port -dir I rx_ref_clk] +set rx_sync [create_bd_port -dir O rx_sync] +set rx_sysref [create_bd_port -dir O rx_sysref] +set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] +set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] + +set mlo_clk [create_bd_port -dir O mlo_clk] + +set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] +set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] +set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] +set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2] +set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3] +set adc_dwr_0 [create_bd_port -dir O adc_dwr_0] +set adc_dwr_1 [create_bd_port -dir O adc_dwr_1] +set adc_dwr_2 [create_bd_port -dir O adc_dwr_2] +set adc_dwr_3 [create_bd_port -dir O adc_dwr_3] +set adc_dsync_0 [create_bd_port -dir O adc_dsync_0] +set adc_dsync_1 [create_bd_port -dir O adc_dsync_1] +set adc_dsync_2 [create_bd_port -dir O adc_dsync_2] +set adc_dsync_3 [create_bd_port -dir O adc_dsync_3] +set adc_ddata_0 [create_bd_port -dir O -from 127 -to 0 adc_ddata_0] +set adc_ddata_1 [create_bd_port -dir O -from 127 -to 0 adc_ddata_1] +set adc_ddata_2 [create_bd_port -dir O -from 127 -to 0 adc_ddata_2] +set adc_ddata_3 [create_bd_port -dir O -from 127 -to 0 adc_ddata_3] +set adc_dovf_0 [create_bd_port -dir I adc_dovf_0] +set adc_dovf_1 [create_bd_port -dir I adc_dovf_1] +set adc_dovf_2 [create_bd_port -dir I adc_dovf_2] +set adc_dovf_3 [create_bd_port -dir I adc_dovf_3] +set adc_dwr [create_bd_port -dir I adc_dwr] +set adc_dsync [create_bd_port -dir I adc_dsync] +set adc_ddata [create_bd_port -dir I -from 511 -to 0 adc_ddata] +set adc_dovf [create_bd_port -dir O adc_dovf] + +# adc peripherals + +set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0] +set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0] + +set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1] +set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1] + +set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2] +set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2] + +set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3] +set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3] + +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_usdrx1_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd +set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd + +set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] +set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] [get_bd_cells axi_usdrx1_gt] +set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {4}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {4}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {4}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt +set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt + +set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {512}] $axi_usdrx1_dma + +set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect + +set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect + +# gpio and spi + +set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi] +set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi + +# additions to default configuration + +set_property -dict [list CONFIG.NUM_MI {15}] $axi_cpu_interconnect +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7 + +set_property LEFT 43 [get_bd_ports GPIO_I] +set_property LEFT 43 [get_bd_ports GPIO_O] +set_property LEFT 43 [get_bd_ports GPIO_T] + +# connections (spi and gpio) + +connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i] +connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o] +connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i] +connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o] +connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i] +connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o] +connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] + +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] + +# connections (gt) + +connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] + +# connections (adc) + +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk] + +connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset] +connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_jesd/rx_sysref] +connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in] +connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in] +connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in] +connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in] +connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done] +connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out] +connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync] +connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame] +connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata] +connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] [get_bd_ports gt_rx_data] +connect_bd_net -net axi_usdrx1_gt_rx_data_0 [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_ports gt_rx_data_0] +connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_ports gt_rx_data_1] +connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2] +connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3] +connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9671_core_adc_dwr_0 [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_ports adc_dwr_0] +connect_bd_net -net axi_ad9671_core_adc_dwr_1 [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_ports adc_dwr_1] +connect_bd_net -net axi_ad9671_core_adc_dwr_2 [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_ports adc_dwr_2] +connect_bd_net -net axi_ad9671_core_adc_dwr_3 [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_ports adc_dwr_3] +connect_bd_net -net axi_ad9671_core_adc_dsync_0 [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_ports adc_dsync_0] +connect_bd_net -net axi_ad9671_core_adc_dsync_1 [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_ports adc_dsync_1] +connect_bd_net -net axi_ad9671_core_adc_dsync_2 [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_ports adc_dsync_2] +connect_bd_net -net axi_ad9671_core_adc_dsync_3 [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_ports adc_dsync_3] +connect_bd_net -net axi_ad9671_core_adc_ddata_0 [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_ports adc_ddata_0] +connect_bd_net -net axi_ad9671_core_adc_ddata_1 [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_ports adc_ddata_1] +connect_bd_net -net axi_ad9671_core_adc_ddata_2 [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_ports adc_ddata_2] +connect_bd_net -net axi_ad9671_core_adc_ddata_3 [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_ports adc_ddata_3] +connect_bd_net -net axi_ad9671_core_adc_dovf_0 [get_bd_pins axi_ad9671_core_0/adc_dovf] [get_bd_ports adc_dovf_0] +connect_bd_net -net axi_ad9671_core_adc_dovf_1 [get_bd_pins axi_ad9671_core_1/adc_dovf] [get_bd_ports adc_dovf_1] +connect_bd_net -net axi_ad9671_core_adc_dovf_2 [get_bd_pins axi_ad9671_core_2/adc_dovf] [get_bd_ports adc_dovf_2] +connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core_3/adc_dovf] [get_bd_ports adc_dovf_3] +connect_bd_net -net axi_ad9671_dma_adc_dwr [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_dwr] +connect_bd_net -net axi_ad9671_dma_adc_dsync [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] [get_bd_ports adc_dsync] +connect_bd_net -net axi_ad9671_dma_adc_ddata [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_ddata] +connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] + +# interconnect (cpu) + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] + +# interconnect (gt es) + +connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi] +connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/m_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/drp_clk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/m_axi_aresetn] + +# interconnect (dma) + +set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] +set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] + +connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source + +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] + +# ila + +set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon + +connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data] +connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] +connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] +connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + +# address map + +create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0 +create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1 +create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2 +create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3 + +create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt +create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd +create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma +create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi + +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm + diff --git a/projects/ad9671_fmc/zc706/system_bd.tcl b/projects/ad9671_fmc/zc706/system_bd.tcl new file mode 100755 index 000000000..8450cffa5 --- /dev/null +++ b/projects/ad9671_fmc/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/usdrx1_bd.tcl + diff --git a/projects/ad9671_fmc/zc706/system_constr.xdc b/projects/ad9671_fmc/zc706/system_constr.xdc new file mode 100755 index 000000000..97392c994 --- /dev/null +++ b/projects/ad9671_fmc/zc706/system_constr.xdc @@ -0,0 +1,97 @@ + +# constraints +# ultrasound + +set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AJ8} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG8} [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7} [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AE8} [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7} [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH6} [get_ports rx_data_p[4]] ; ## A14 FMC_HPC_DP4_M2C_P +set_property -dict {PACKAGE_PIN AH5} [get_ports rx_data_n[4]] ; ## A15 FMC_HPC_DP4_M2C_N +set_property -dict {PACKAGE_PIN AG4} [get_ports rx_data_p[5]] ; ## A18 FMC_HPC_DP5_M2C_P +set_property -dict {PACKAGE_PIN AG3} [get_ports rx_data_n[5]] ; ## A19 FMC_HPC_DP5_M2C_N +set_property -dict {PACKAGE_PIN AF6} [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P +set_property -dict {PACKAGE_PIN AF5} [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N +set_property -dict {PACKAGE_PIN AD6} [get_ports rx_data_p[7]] ; ## B12 FMC_HPC_DP7_M2C_P +set_property -dict {PACKAGE_PIN AD5} [get_ports rx_data_n[7]] ; ## B13 FMC_HPC_DP7_M2C_N +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25} [get_ports rx_sysref_p] ; ## D23 FMC_HPC_LA23_P +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVDS_25} [get_ports rx_sysref_n] ; ## D24 FMC_HPC_LA23_N +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D26 FMC_HPC_LA26_P +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D27 FMC_HPC_LA26_N +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports afe_mlo_p] ; ## D20 FMC_HPC_LA17_CC_P +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports afe_mlo_n] ; ## D21 FMC_HPC_LA17_CC_N +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports afe_rst_p] ; ## G27 FMC_HPC_LA25_P +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports afe_rst_n] ; ## G28 FMC_HPC_LA25_N +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25} [get_ports afe_trig_p] ; ## H28 FMC_HPC_LA24_P +set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25} [get_ports afe_trig_n] ; ## H29 FMC_HPC_LA24_N + +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_clk] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_mlo] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_rst] ; ## C18 FMC_HPC_LA14_P +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sync] ; ## C19 FMC_HPC_LA14_N +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_sysref] ; ## C22 FMC_HPC_LA18_CC_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_fout_enb_trig] ; ## C23 FMC_HPC_LA18_CC_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_fout_clk] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports spi_fout_sdio] ; ## C11 FMC_HPC_LA06_N + +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[0]] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[1]] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[2]] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_afe_csn[3]] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_afe_clk] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_afe_sdio] ; ## D09 FMC_HPC_LA01_CC_N + +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G12 FMC_HPC_LA08_P + +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports afe_pdn] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports afe_stby] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports clk_resetn] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports clk_syncn] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports clk_status] ; ## G18 FMC_HPC_LA16_P + +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports amp_disbn] ; ## G19 FMC_HPC_LA16_N +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports prc_sck] ; ## G21 FMC_HPC_LA20_P +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports prc_cnv] ; ## G22 FMC_HPC_LA20_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports prc_sdo_i] ; ## G24 FMC_HPC_LA22_P +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports prc_sdo_q] ; ## G25 FMC_HPC_LA22_N + +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports dac_sleep] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports dac_data[0]] ; ## H26 FMC_HPC_LA21_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports dac_data[1]] ; ## H25 FMC_HPC_LA21_P +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports dac_data[2]] ; ## H23 FMC_HPC_LA19_N +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports dac_data[3]] ; ## H22 FMC_HPC_LA19_P +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports dac_data[4]] ; ## H20 FMC_HPC_LA15_N +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports dac_data[5]] ; ## H19 FMC_HPC_LA15_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports dac_data[6]] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports dac_data[7]] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports dac_data[8]] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports dac_data[9]] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports dac_data[10]] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports dac_data[11]] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports dac_data[12]] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data[13]] ; ## H07 FMC_HPC_LA02_P + +# clocks + +create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3] + +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/ad9671_fmc/zc706/system_project.tcl b/projects/ad9671_fmc/zc706/system_project.tcl new file mode 100755 index 000000000..1a01c2578 --- /dev/null +++ b/projects/ad9671_fmc/zc706/system_project.tcl @@ -0,0 +1,16 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create usdrx1_zc706 +adi_project_files usdrx1_zc706 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "../common/usdrx1_spi.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run usdrx1_zc706 + + diff --git a/projects/ad9671_fmc/zc706/system_top.v b/projects/ad9671_fmc/zc706/system_top.v new file mode 100755 index 000000000..6979d7c62 --- /dev/null +++ b/projects/ad9671_fmc/zc706/system_top.v @@ -0,0 +1,477 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + spi_fout_enb_clk, + spi_fout_enb_mlo, + spi_fout_enb_rst, + spi_fout_enb_sync, + spi_fout_enb_sysref, + spi_fout_enb_trig, + spi_fout_clk, + spi_fout_sdio, + spi_afe_csn, + spi_afe_clk, + spi_afe_sdio, + spi_clk_csn, + spi_clk_clk, + spi_clk_sdio, + + afe_mlo_p, + afe_mlo_n, + afe_rst_p, + afe_rst_n, + afe_trig_p, + afe_trig_n, + + dac_sleep, + dac_data, + afe_pdn, + afe_stby, + clk_resetn, + clk_syncn, + clk_status, + amp_disbn, + prc_sck, + prc_cnv, + prc_sdo_i, + prc_sdo_q); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + output rx_sysref_p; + output rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 7:0] rx_data_p; + input [ 7:0] rx_data_n; + + output spi_fout_enb_clk; + output spi_fout_enb_mlo; + output spi_fout_enb_rst; + output spi_fout_enb_sync; + output spi_fout_enb_sysref; + output spi_fout_enb_trig; + output spi_fout_clk; + inout spi_fout_sdio; + output [ 3:0] spi_afe_csn; + output spi_afe_clk; + inout spi_afe_sdio; + output spi_clk_csn; + output spi_clk_clk; + inout spi_clk_sdio; + + output afe_mlo_p; + output afe_mlo_n; + output afe_rst_p; + output afe_rst_n; + output afe_trig_p; + output afe_trig_n; + + inout dac_sleep; + inout [13:0] dac_data; + inout afe_pdn; + inout afe_stby; + inout clk_resetn; + inout clk_syncn; + inout clk_status; + inout amp_disbn; + inout prc_sck; + inout prc_cnv; + inout prc_sdo_i; + inout prc_sdo_q; + + // internal signals + + wire [43:0] gpio_i; + wire [43:0] gpio_o; + wire [43:0] gpio_t; + wire [10:0] spi_csn; + wire afe_mlo; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire [ 1:0] gpio_open; + + wire [511:0] adc_ddata; + wire [127:0] adc_ddata_0; + wire [127:0] adc_ddata_1; + wire [127:0] adc_ddata_2; + wire [127:0] adc_ddata_3; + wire adc_dovf; + wire adc_dovf_0; + wire adc_dovf_1; + wire adc_dovf_2; + wire adc_dovf_3; + wire adc_dsync; + wire adc_dsync_0; + wire adc_dsync_1; + wire adc_dsync_2; + wire adc_dsync_3; + wire adc_dwr; + wire adc_dwr_0; + wire adc_dwr_1; + wire adc_dwr_2; + wire adc_dwr_3; + wire [255:0] gt_rx_data; + wire [63:0] gt_rx_data_0; + wire [63:0] gt_rx_data_1; + wire [63:0] gt_rx_data_2; + wire [63:0] gt_rx_data_3; + + // spi assignments + + assign spi_fout_enb_clk = spi_csn[10:10]; + assign spi_fout_enb_mlo = spi_csn[ 9: 9]; + assign spi_fout_enb_rst = spi_csn[ 8: 8]; + assign spi_fout_enb_sync = spi_csn[ 7: 7]; + assign spi_fout_enb_sysref = spi_csn[ 6: 6]; + assign spi_fout_enb_trig = spi_csn[ 5: 5]; + assign spi_afe_csn = spi_csn[ 4: 1]; + assign spi_clk_csn = spi_csn[ 0: 0]; + + assign spi_fout_clk = spi_clk; + assign spi_afe_clk = spi_clk; + assign spi_clk_clk = spi_clk; + + // single dma for all channels + + assign gt_rx_data_3 = gt_rx_data[255:192]; + assign gt_rx_data_2 = gt_rx_data[191:128]; + assign gt_rx_data_1 = gt_rx_data[127: 64]; + assign gt_rx_data_0 = gt_rx_data[ 63: 0]; + + assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0; + assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0; + assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0}; + + assign adc_dovf_0 = adc_dovf; + assign adc_dovf_1 = adc_dovf; + assign adc_dovf_2 = adc_dovf; + assign adc_dovf_3 = adc_dovf; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sysref ( + .I (rx_sysref), + .O (rx_sysref_p), + .OB (rx_sysref_n)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + OBUFDS i_obufds_mlo ( + .I (afe_mlo), + .O (afe_mlo_p), + .OB (afe_mlo_n)); + + IOBUF i_iobuf_gpio_prc_sdo_q ( + .I (gpio_o[43]), + .O (gpio_i[43]), + .T (gpio_t[43]), + .IO (prc_sdo_q)); + + IOBUF i_iobuf_gpio_prc_sdo_i ( + .I (gpio_o[42]), + .O (gpio_i[42]), + .T (gpio_t[42]), + .IO (prc_sdo_i)); + + IOBUF i_iobuf_gpio_prc_cnv ( + .I (gpio_o[41]), + .O (gpio_i[41]), + .T (gpio_t[41]), + .IO (prc_cnv)); + + IOBUF i_iobuf_gpio_prc_sck ( + .I (gpio_o[40]), + .O (gpio_i[40]), + .T (gpio_t[40]), + .IO (prc_sck)); + + IOBUF i_iobuf_gpio_amp_disbn ( + .I (gpio_o[39]), + .O (gpio_i[39]), + .T (gpio_t[39]), + .IO (amp_disbn)); + + IOBUF i_iobuf_gpio_clk_status ( + .I (gpio_o[38]), + .O (gpio_i[38]), + .T (gpio_t[38]), + .IO (clk_status)); + + IOBUF i_iobuf_gpio_clk_syncn ( + .I (gpio_o[37]), + .O (gpio_i[37]), + .T (gpio_t[37]), + .IO (clk_syncn)); + + IOBUF i_iobuf_gpio_clk_resetn ( + .I (gpio_o[36]), + .O (gpio_i[36]), + .T (gpio_t[36]), + .IO (clk_resetn)); + + IOBUF i_iobuf_gpio_afe_stby ( + .I (gpio_o[35]), + .O (gpio_i[35]), + .T (gpio_t[35]), + .IO (afe_stby)); + + IOBUF i_iobuf_gpio_afe_pdn ( + .I (gpio_o[34]), + .O (gpio_i[34]), + .T (gpio_t[34]), + .IO (afe_pdn)); + + OBUFDS i_obufds_gpio_afe_trig ( + .I (gpio_o[33]), + .O (afe_trig_p), + .OB (afe_trig_n)); + + OBUFDS i_obufds_gpio_afe_rst ( + .I (gpio_o[32]), + .O (afe_rst_p), + .OB (afe_rst_n)); + + IOBUF i_iobuf_gpio_dac_sleep ( + .I (gpio_o[30]), + .O (gpio_i[30]), + .T (gpio_t[30]), + .IO (dac_sleep)); + + genvar n; + generate + for (n = 0; n <= 13; n = n + 1) begin: g_iobuf_gpio_dac_data + IOBUF i_iobuf_gpio_dac_data ( + .I (gpio_o[16+n]), + .O (gpio_i[16+n]), + .T (gpio_t[16+n]), + .IO (dac_data[n])); + end + for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + usdrx1_spi i_spi ( + .spi_fout_csn (spi_csn[10:5]), + .spi_afe_csn (spi_csn[4:1]), + .spi_clk_csn (spi_csn[0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_fout_sdio (spi_fout_sdio), + .spi_afe_sdio (spi_afe_sdio), + .spi_clk_sdio (spi_clk_sdio)); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .adc_ddata (adc_ddata), + .adc_ddata_0 (adc_ddata_0), + .adc_ddata_1 (adc_ddata_1), + .adc_ddata_2 (adc_ddata_2), + .adc_ddata_3 (adc_ddata_3), + .adc_dovf (adc_dovf), + .adc_dovf_0 (adc_dovf_0), + .adc_dovf_1 (adc_dovf_1), + .adc_dovf_2 (adc_dovf_2), + .adc_dovf_3 (adc_dovf_3), + .adc_dsync (adc_dsync), + .adc_dsync_0 (adc_dsync_0), + .adc_dsync_1 (adc_dsync_1), + .adc_dsync_2 (adc_dsync_2), + .adc_dsync_3 (adc_dsync_3), + .adc_dwr (adc_dwr), + .adc_dwr_0 (adc_dwr_0), + .adc_dwr_1 (adc_dwr_1), + .adc_dwr_2 (adc_dwr_2), + .adc_dwr_3 (adc_dwr_3), + .gt_rx_data (gt_rx_data), + .gt_rx_data_0 (gt_rx_data_0), + .gt_rx_data_1 (gt_rx_data_1), + .gt_rx_data_2 (gt_rx_data_2), + .gt_rx_data_3 (gt_rx_data_3), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .mlo_clk (afe_mlo), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi)); + +endmodule + +// *************************************************************************** +// ***************************************************************************