dma: moved
Rejeesh Kutty
parent
9fa3131858
commit
7224ca1f0c
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@ -0,0 +1,156 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module fifo_address_gray (
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output reg m_axis_valid,
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output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
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input s_axis_aclk,
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input s_axis_aresetn,
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output reg s_axis_ready,
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input s_axis_valid,
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output reg s_axis_empty,
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output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
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);
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parameter C_ADDRESS_WIDTH = 4;
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reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
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reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
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reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
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reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
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reg [C_ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
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wire [C_ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
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wire [C_ADDRESS_WIDTH:0] s_axis_raddr_gray;
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reg [C_ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
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wire [C_ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
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wire [C_ADDRESS_WIDTH:0] m_axis_waddr_gray;
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assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
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assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
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always @(*)
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begin
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if (s_axis_ready && s_axis_valid)
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_s_axis_waddr_next <= _s_axis_waddr + 1;
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else
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_s_axis_waddr_next <= _s_axis_waddr;
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end
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assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[C_ADDRESS_WIDTH:1];
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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_s_axis_waddr <= 'h00;
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s_axis_waddr_gray <= 'h00;
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end else begin
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_s_axis_waddr <= _s_axis_waddr_next;
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s_axis_waddr_gray <= s_axis_waddr_gray_next;
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end
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end
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always @(*)
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begin
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if (m_axis_ready && m_axis_valid)
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_m_axis_raddr_next <= _m_axis_raddr + 1;
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else
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_m_axis_raddr_next <= _m_axis_raddr;
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end
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assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[C_ADDRESS_WIDTH:1];
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always @(posedge m_axis_aclk)
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begin
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if (m_axis_aresetn == 1'b0) begin
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_m_axis_raddr <= 'h00;
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m_axis_raddr_gray <= 'h00;
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end else begin
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_m_axis_raddr <= _m_axis_raddr_next;
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m_axis_raddr_gray <= m_axis_raddr_gray_next;
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end
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end
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sync_bits #(
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.NUM_BITS(C_ADDRESS_WIDTH + 1)
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) i_waddr_sync (
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.out_clk(m_axis_aclk),
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.out_resetn(m_axis_aresetn),
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.in(s_axis_waddr_gray),
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.out(m_axis_waddr_gray)
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);
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sync_bits #(
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.NUM_BITS(C_ADDRESS_WIDTH + 1)
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) i_raddr_sync (
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.out_clk(s_axis_aclk),
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.out_resetn(s_axis_aresetn),
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.in(m_axis_raddr_gray),
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.out(s_axis_raddr_gray)
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);
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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s_axis_ready <= 1'b1;
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s_axis_empty <= 1'b1;
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end else begin
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s_axis_ready <= (s_axis_raddr_gray[C_ADDRESS_WIDTH] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH] ||
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s_axis_raddr_gray[C_ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH-1] ||
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s_axis_raddr_gray[C_ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[C_ADDRESS_WIDTH-2:0]);
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s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
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end
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end
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always @(posedge m_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0)
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m_axis_valid <= 1'b0;
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else begin
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m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
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end
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end
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endmodule
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@ -0,0 +1,147 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module fifo_address_gray_pipelined (
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output reg m_axis_valid,
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output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
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output [C_ADDRESS_WIDTH-1:0] m_axis_raddr,
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input s_axis_aclk,
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input s_axis_aresetn,
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output reg s_axis_ready,
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input s_axis_valid,
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output reg s_axis_empty,
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output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
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);
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parameter C_ADDRESS_WIDTH = 4;
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reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
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reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
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wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
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reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
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reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
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wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
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assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
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assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
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assign m_axis_raddr = _m_axis_raddr[C_ADDRESS_WIDTH-1:0];
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always @(*)
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begin
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if (s_axis_ready && s_axis_valid)
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_s_axis_waddr_next <= _s_axis_waddr + 1;
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else
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_s_axis_waddr_next <= _s_axis_waddr;
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end
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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_s_axis_waddr <= 'h00;
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end else begin
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_s_axis_waddr <= _s_axis_waddr_next;
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end
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end
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always @(*)
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begin
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if (m_axis_ready && m_axis_valid)
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_m_axis_raddr_next <= _m_axis_raddr + 1;
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else
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_m_axis_raddr_next <= _m_axis_raddr;
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end
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always @(posedge m_axis_aclk)
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begin
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if (m_axis_aresetn == 1'b0) begin
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_m_axis_raddr <= 'h00;
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end else begin
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_m_axis_raddr <= _m_axis_raddr_next;
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end
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end
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sync_gray #(
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.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
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) i_waddr_sync (
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.in_clk(s_axis_aclk),
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.in_resetn(s_axis_aresetn),
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.out_clk(m_axis_aclk),
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.out_resetn(m_axis_aresetn),
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.in_count(_s_axis_waddr),
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.out_count(_m_axis_waddr)
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);
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sync_gray #(
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.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
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) i_raddr_sync (
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.in_clk(m_axis_aclk),
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.in_resetn(m_axis_aresetn),
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.out_clk(s_axis_aclk),
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.out_resetn(s_axis_aresetn),
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.in_count(_m_axis_raddr),
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.out_count(_s_axis_raddr)
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);
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always @(posedge s_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0) begin
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s_axis_ready <= 1'b1;
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s_axis_empty <= 1'b1;
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end else begin
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s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
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_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
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s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
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end
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end
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always @(posedge m_axis_aclk)
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begin
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if (s_axis_aresetn == 1'b0)
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m_axis_valid <= 1'b0;
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else begin
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m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
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end
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end
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endmodule
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@ -0,0 +1,106 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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// Author: Lars-Peter Clausen <lars@metafoo.de>
|
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//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
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// ***************************************************************************
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module fifo_address_sync (
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input clk,
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input resetn,
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input m_axis_ready,
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output reg m_axis_valid,
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output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr,
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output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
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output reg s_axis_ready,
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input s_axis_valid,
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output reg s_axis_empty,
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output reg [C_ADDRESS_WIDTH-1:0] s_axis_waddr
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);
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parameter C_ADDRESS_WIDTH = 4;
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reg [C_ADDRESS_WIDTH:0] level;
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reg [C_ADDRESS_WIDTH:0] level_next;
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wire read = m_axis_ready & m_axis_valid;
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wire write = s_axis_ready & s_axis_valid;
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always @(*)
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begin
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if (read)
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m_axis_raddr_next <= m_axis_raddr + 1'b1;
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else
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m_axis_raddr_next <= m_axis_raddr;
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end
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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s_axis_waddr <= 'h00;
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m_axis_raddr <= 'h00;
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end else begin
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if (write)
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s_axis_waddr <= s_axis_waddr + 1'b1;
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m_axis_raddr <= m_axis_raddr_next;
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end
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end
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always @(*)
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begin
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if (read & ~write)
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level_next <= level - 1'b1;
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else if (~read & write)
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level_next <= level + 1'b1;
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else
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level_next <= level;
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end
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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m_axis_valid <= 1'b0;
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s_axis_ready <= 1'b0;
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end else begin
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level <= level_next;
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m_axis_valid <= level_next != 0;
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s_axis_ready <= level_next != 2**C_ADDRESS_WIDTH;
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s_axis_empty <= level_next == 0;
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end
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end
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endmodule
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@ -8,10 +8,10 @@ adi_ip_files axi_dmac [list \
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"$ad_hdl_dir/library/common/sync_bits.v" \
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"$ad_hdl_dir/library/common/sync_gray.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/axi_fifo/axi_fifo.v" \
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"$ad_hdl_dir/library/axi_fifo/address_gray.v" \
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"$ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v" \
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"$ad_hdl_dir/library/axi_fifo/address_sync.v" \
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"fifo.v" \
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"address_gray.v" \
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"address_gray_pipelined.v" \
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"address_sync.v" \
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"address_generator.v" \
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"data_mover.v" \
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"request_arb.v" \
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|
|
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|
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@ -0,0 +1,196 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2013(c) Analog Devices, Inc.
|
||||
// Author: Lars-Peter Clausen <lars@metafoo.de>
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
module fifo (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [C_DATA_WIDTH-1:0] m_axis_data,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [C_DATA_WIDTH-1:0] s_axis_data,
|
||||
output s_axis_empty
|
||||
);
|
||||
|
||||
parameter C_DATA_WIDTH = 64;
|
||||
parameter C_CLKS_ASYNC = 1;
|
||||
parameter C_ADDRESS_WIDTH = 4;
|
||||
|
||||
generate if (C_ADDRESS_WIDTH == 0) begin
|
||||
|
||||
reg [C_DATA_WIDTH-1:0] ram;
|
||||
reg s_axis_waddr = 1'b0;
|
||||
reg m_axis_raddr = 1'b0;
|
||||
|
||||
wire m_axis_waddr;
|
||||
wire s_axis_raddr;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_BITS(1),
|
||||
.CLK_ASYNC(C_CLKS_ASYNC)
|
||||
) i_waddr_sync (
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in(s_axis_waddr),
|
||||
.out(m_axis_waddr)
|
||||
);
|
||||
|
||||
sync_bits #(
|
||||
.NUM_BITS(1),
|
||||
.CLK_ASYNC(C_CLKS_ASYNC)
|
||||
) i_raddr_sync (
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in(m_axis_raddr),
|
||||
.out(s_axis_raddr)
|
||||
);
|
||||
|
||||
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
|
||||
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
|
||||
assign s_axis_empty = s_axis_raddr == s_axis_waddr;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready)
|
||||
ram <= s_axis_data;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_waddr <= 1'b0;
|
||||
end else begin
|
||||
if (s_axis_ready & s_axis_valid) begin
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_raddr <= 1'b0;
|
||||
end else begin
|
||||
if (m_axis_valid & m_axis_ready)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = ram;
|
||||
|
||||
end else begin
|
||||
|
||||
reg [C_DATA_WIDTH-1:0] ram[0:2**C_ADDRESS_WIDTH-1];
|
||||
|
||||
wire [C_ADDRESS_WIDTH-1:0] s_axis_waddr;
|
||||
wire [C_ADDRESS_WIDTH-1:0] m_axis_raddr;
|
||||
wire _m_axis_ready;
|
||||
wire _m_axis_valid;
|
||||
|
||||
if (C_CLKS_ASYNC == 1) begin
|
||||
|
||||
fifo_address_gray_pipelined #(
|
||||
.C_ADDRESS_WIDTH(C_ADDRESS_WIDTH)
|
||||
) i_address_gray (
|
||||
.m_axis_aclk(m_axis_aclk),
|
||||
.m_axis_aresetn(m_axis_aresetn),
|
||||
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
|
||||
.s_axis_aclk(s_axis_aclk),
|
||||
.s_axis_aresetn(s_axis_aresetn),
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
fifo_address_sync #(
|
||||
.C_ADDRESS_WIDTH(C_ADDRESS_WIDTH)
|
||||
) i_address_sync (
|
||||
.clk(m_axis_aclk),
|
||||
.resetn(m_axis_aresetn),
|
||||
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready)
|
||||
ram[s_axis_waddr] <= s_axis_data;
|
||||
end
|
||||
|
||||
reg [C_DATA_WIDTH-1:0] data;
|
||||
reg valid;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
if (_m_axis_valid)
|
||||
valid <= 1'b1;
|
||||
else if (m_axis_ready)
|
||||
valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (~valid || m_axis_ready)
|
||||
data <= ram[m_axis_raddr];
|
||||
end
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_data = data;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -819,7 +819,7 @@ axi_repack #(
|
|||
.m_data(src_fifo_repacked_data)
|
||||
);
|
||||
|
||||
axi_fifo #(
|
||||
fifo #(
|
||||
.C_DATA_WIDTH(DMA_DATA_WIDTH),
|
||||
.C_ADDRESS_WIDTH($clog2(C_MAX_BYTES_PER_BURST / (DMA_DATA_WIDTH / 8) * C_FIFO_SIZE)),
|
||||
.C_CLKS_ASYNC(C_CLKS_ASYNC_SRC_DEST)
|
||||
|
|
@ -924,7 +924,7 @@ splitter #(
|
|||
})
|
||||
);
|
||||
|
||||
axi_fifo #(
|
||||
fifo #(
|
||||
.C_DATA_WIDTH(DMA_ADDR_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + C_BYTES_PER_BEAT_WIDTH_DEST),
|
||||
.C_ADDRESS_WIDTH(0),
|
||||
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
|
||||
|
|
@ -950,7 +950,7 @@ axi_fifo #(
|
|||
})
|
||||
);
|
||||
|
||||
axi_fifo #(
|
||||
fifo #(
|
||||
.C_DATA_WIDTH(DMA_ADDR_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
|
||||
.C_ADDRESS_WIDTH(0),
|
||||
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
|
||||
|
|
@ -976,7 +976,7 @@ axi_fifo #(
|
|||
})
|
||||
);
|
||||
|
||||
axi_fifo #(
|
||||
fifo #(
|
||||
.C_DATA_WIDTH(3),
|
||||
.C_ADDRESS_WIDTH(0),
|
||||
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
|
||||
|
|
@ -994,7 +994,7 @@ axi_fifo #(
|
|||
.m_axis_data(response_dest_resp_eot)
|
||||
);
|
||||
|
||||
axi_fifo #(
|
||||
fifo #(
|
||||
.C_DATA_WIDTH(2),
|
||||
.C_ADDRESS_WIDTH(0),
|
||||
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
|
||||
|
|
|
|||
Loading…
Reference in New Issue