axi_ad9361: Grup interfaces to add support for more carriers

library/axi_ad9361/axi_ad9361_ip.tcl

@@ -34,8 +34,8 @@ adi_ip_files axi_ad9361 [list \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
   "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
   "axi_ad9361_constr.xdc" \
-  "axi_ad9361_lvds_if.v" \
-  "axi_ad9361_cmos_if.v" \
+  "xilinx/axi_ad9361_lvds_if.v" \
+  "xilinx/axi_ad9361_cmos_if.v" \
   "axi_ad9361_rx_pnmon.v" \
   "axi_ad9361_rx_channel.v" \
   "axi_ad9361_rx.v" \

library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v

@@ -103,7 +103,17 @@ module axi_ad9361_lvds_if (
   up_dac_drdata,
   delay_clk,
   delay_rst,
-  delay_locked);
+  delay_locked,
+
+  //drp interface
+
+  up_drp_sel,
+  up_drp_wr,
+  up_drp_addr,
+  up_drp_wdata,
+  up_drp_rdata,
+  up_drp_ready,
+  up_drp_locked);
 
   // this parameter controls the buffer type based on the target device.
 
@@ -177,6 +187,16 @@ module axi_ad9361_lvds_if (
   input           delay_rst;
   output          delay_locked;
 
+  //drp interface
+
+  input               up_drp_sel;
+  input               up_drp_wr;
+  input   [11:0]      up_drp_addr;
+  input   [31:0]      up_drp_wdata;
+  output  [31:0]      up_drp_rdata;
+  output              up_drp_ready;
+  output              up_drp_locked;
+
   // internal registers
 
   reg     [ 5:0]  rx_data_p = 0;
@@ -245,6 +265,12 @@ module axi_ad9361_lvds_if (
   wire            rx_frame_n_s;
   wire            locked_s;
 
+  // drp interface signals
+
+  assign up_drp_rdata = 32'd0;
+  assign up_drp_ready = 1'd0;
+  assign up_drp_locked = 1'd1;
+
   genvar          l_inst;
 
   // receive data path interface
@@ -633,6 +659,14 @@ module axi_ad9361_lvds_if (
     .clk_in_n (rx_clk_in_n),
     .clk (l_clk));
 
+  // debug
+	ila_TEST_DAC_MODE ila_dac_mode (
+	.clk(clk),
+	.probe0(dac_r1_mode),
+	.probe1(dac_valid));
+
+// end debug
+
 endmodule
 
 // ***************************************************************************