axi_ad9361: Grup interfaces to add support for more carriers
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5bb77109ca
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@ -34,8 +34,8 @@ adi_ip_files axi_ad9361 [list \
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"$ad_hdl_dir/library/common/up_dac_channel.v" \
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"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
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"axi_ad9361_constr.xdc" \
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"axi_ad9361_lvds_if.v" \
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"axi_ad9361_cmos_if.v" \
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"xilinx/axi_ad9361_lvds_if.v" \
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"xilinx/axi_ad9361_cmos_if.v" \
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"axi_ad9361_rx_pnmon.v" \
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"axi_ad9361_rx_channel.v" \
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"axi_ad9361_rx.v" \
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -103,7 +103,17 @@ module axi_ad9361_lvds_if (
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up_dac_drdata,
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delay_clk,
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delay_rst,
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delay_locked);
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delay_locked,
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//drp interface
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up_drp_sel,
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up_drp_wr,
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up_drp_addr,
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up_drp_wdata,
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up_drp_rdata,
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up_drp_ready,
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up_drp_locked);
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// this parameter controls the buffer type based on the target device.
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@ -177,6 +187,16 @@ module axi_ad9361_lvds_if (
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input delay_rst;
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output delay_locked;
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//drp interface
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input up_drp_sel;
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input up_drp_wr;
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input [11:0] up_drp_addr;
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input [31:0] up_drp_wdata;
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output [31:0] up_drp_rdata;
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output up_drp_ready;
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output up_drp_locked;
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// internal registers
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reg [ 5:0] rx_data_p = 0;
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@ -245,6 +265,12 @@ module axi_ad9361_lvds_if (
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wire rx_frame_n_s;
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wire locked_s;
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// drp interface signals
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assign up_drp_rdata = 32'd0;
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assign up_drp_ready = 1'd0;
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assign up_drp_locked = 1'd1;
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genvar l_inst;
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// receive data path interface
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@ -633,6 +659,14 @@ module axi_ad9361_lvds_if (
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.clk_in_n (rx_clk_in_n),
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.clk (l_clk));
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// debug
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ila_TEST_DAC_MODE ila_dac_mode (
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.clk(clk),
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.probe0(dac_r1_mode),
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.probe1(dac_valid));
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// end debug
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endmodule
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// ***************************************************************************
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