axi_adrv9001: Add opt-in synthesis parameters
parent
31929167d3
commit
714d557245
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@ -39,6 +39,9 @@ module axi_adrv9001 #(
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parameter ID = 0,
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parameter CMOS_LVDS_N = 0,
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parameter TDD_DISABLE = 0,
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parameter DDS_DISABLE = 0,
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parameter INDEPENDENT_1R1T_SUPPORT = 1,
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parameter COMMON_2R2T_SUPPORT = 1,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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@ -376,6 +379,9 @@ module axi_adrv9001 #(
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.DRP_WIDTH (DRP_WIDTH),
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.TDD_DISABLE (TDD_DISABLE),
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.DDS_DISABLE (DDS_DISABLE),
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.INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT),
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.COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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@ -41,6 +41,9 @@ module axi_ad9001_core #(
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parameter NUM_LANES = 3,
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parameter DRP_WIDTH = 5,
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parameter TDD_DISABLE = 0,
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parameter DDS_DISABLE = 0,
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parameter INDEPENDENT_1R1T_SUPPORT = 1,
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parameter COMMON_2R2T_SUPPORT = 1,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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@ -262,10 +265,11 @@ module axi_ad9001_core #(
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axi_adrv9001_rx #(
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.ID (ID),
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.ENABLED (1),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.COMMON_BASE_ADDR(6'h00),
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.CHANNEL_BASE_ADDR(6'h01),
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.MODE_R1 (0),
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.MODE_R1 (COMMON_2R2T_SUPPORT==0),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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@ -321,6 +325,7 @@ module axi_ad9001_core #(
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axi_adrv9001_rx #(
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.ID (ID),
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.ENABLED (INDEPENDENT_1R1T_SUPPORT),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.COMMON_BASE_ADDR(6'h04),
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.CHANNEL_BASE_ADDR(6'h05),
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@ -374,15 +379,16 @@ module axi_ad9001_core #(
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axi_adrv9001_tx #(
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.ID (ID),
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.ENABLED (1),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.COMMON_BASE_ADDR ('h08),
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.CHANNEL_BASE_ADDR ('h09),
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.MODE_R1 (0),
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.MODE_R1 (COMMON_2R2T_SUPPORT==0),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.DDS_DISABLE (0),
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.DDS_DISABLE (DDS_DISABLE),
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.IQCORRECTION_DISABLE (1),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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@ -425,6 +431,7 @@ module axi_ad9001_core #(
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axi_adrv9001_tx #(
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.ID (ID),
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.ENABLED (INDEPENDENT_1R1T_SUPPORT),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.COMMON_BASE_ADDR ('h10),
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.CHANNEL_BASE_ADDR ('h11),
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@ -433,7 +440,7 @@ module axi_ad9001_core #(
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.DDS_DISABLE (0),
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.DDS_DISABLE (DDS_DISABLE),
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.IQCORRECTION_DISABLE (1),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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@ -37,6 +37,7 @@
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module axi_adrv9001_rx #(
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parameter ID = 0,
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parameter ENABLED = 1,
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parameter CMOS_LVDS_N = 0,
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parameter COMMON_BASE_ADDR = 'h00,
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parameter CHANNEL_BASE_ADDR = 'h01,
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@ -101,6 +102,31 @@ module axi_adrv9001_rx #(
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output reg up_rack
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);
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generate
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if (ENABLED == 0) begin : core_disabled
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assign adc_rst = 1'b0;
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assign adc_single_lane = 1'b0;
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assign adc_sdr_ddr_n = 1'b0;
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assign adc_r1_mode = 1'b0;
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assign adc_valid = 1'b0;
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assign adc_enable_i0 = 1'b0;
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assign adc_data_i0 = 16'b0;
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assign adc_enable_q0 = 1'b0;
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assign adc_data_q0 = 16'b0;
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assign adc_enable_i1 = 1'b0;
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assign adc_data_i1 = 16'b0;
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assign adc_enable_q1 = 1'b0;
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assign adc_data_q1 = 16'b0;
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always @(*) begin
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up_wack = 1'b0;
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up_rdata = 32'b0;
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up_rack = 1'b0;
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end
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end else begin : core_enabled
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// configuration settings
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localparam CONFIG = (CMOS_LVDS_N * 128) +
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@ -366,6 +392,9 @@ module axi_adrv9001_rx #(
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assign adc_single_lane = adc_num_lanes[0];
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end
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endgenerate
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endmodule
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// ***************************************************************************
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@ -37,6 +37,7 @@
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module axi_adrv9001_tx #(
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parameter ID = 0,
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parameter ENABLED = 1,
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parameter CMOS_LVDS_N = 0,
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parameter COMMON_BASE_ADDR = 'h10,
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parameter CHANNEL_BASE_ADDR = 'h11,
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@ -100,6 +101,33 @@ module axi_adrv9001_tx #(
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output reg [ 31:0] up_rdata,
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output reg up_rack
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);
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generate
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if (ENABLED == 0) begin : core_disabled
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assign dac_rst = 1'b0;
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assign dac_data_valid_A = 1'b0;
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assign dac_data_i_A = 16'b0;
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assign dac_data_q_A = 16'b0;
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assign dac_data_valid_B = 1'b0;
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assign dac_data_i_B = 16'b0;
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assign dac_data_q_B = 16'b0;
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assign dac_single_lane = 1'b0;
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assign dac_sdr_ddr_n = 1'b0;
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assign dac_r1_mode = 1'b0;
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assign dac_sync_out = 1'b0;
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assign dac_valid = 1'b0;
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assign dac_enable_i0 = 1'b0;
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assign dac_enable_q0 = 1'b0;
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assign dac_enable_i1 = 1'b0;
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assign dac_enable_q1 = 1'b0;
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always @(*) begin
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up_wack = 1'b0;
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up_rdata = 32'b0;
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up_rack = 1'b0;
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end
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end else begin : core_enabled
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// configuration settings
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@ -377,6 +405,9 @@ module axi_adrv9001_tx #(
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assign dac_single_lane = dac_num_lanes[0];
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end
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endgenerate
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endmodule
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// ***************************************************************************
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