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axi_adrv9001: Add opt-in synthesis parameters

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Laszlo Nagy 2020-12-02 13:50:03 +00:00 committed by Laszlo Nagy
parent 31929167d3
commit 714d557245
4 changed files with 77 additions and 4 deletions
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6
library/axi_adrv9001/axi_adrv9001.v
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@ -39,6 +39,9 @@ module axi_adrv9001 #(
parameter ID = 0,
parameter CMOS_LVDS_N = 0,
parameter TDD_DISABLE = 0,
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
@ -376,6 +379,9 @@ module axi_adrv9001 #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.DRP_WIDTH (DRP_WIDTH),
.TDD_DISABLE (TDD_DISABLE),
.DDS_DISABLE (DDS_DISABLE),
.INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT),
.COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),

15
library/axi_adrv9001/axi_adrv9001_core.v
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@ -41,6 +41,9 @@ module axi_ad9001_core #(
parameter NUM_LANES = 3,
parameter DRP_WIDTH = 5,
parameter TDD_DISABLE = 0,
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -262,10 +265,11 @@ module axi_ad9001_core #(
axi_adrv9001_rx #(
.ID (ID),
.ENABLED (1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h00),
.CHANNEL_BASE_ADDR(6'h01),
.MODE_R1 (0),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -321,6 +325,7 @@ module axi_ad9001_core #(
axi_adrv9001_rx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h04),
.CHANNEL_BASE_ADDR(6'h05),
@ -374,15 +379,16 @@ module axi_ad9001_core #(
axi_adrv9001_tx #(
.ID (ID),
.ENABLED (1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR ('h08),
.CHANNEL_BASE_ADDR ('h09),
.MODE_R1 (0),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DDS_DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
@ -425,6 +431,7 @@ module axi_ad9001_core #(
axi_adrv9001_tx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR ('h10),
.CHANNEL_BASE_ADDR ('h11),
@ -433,7 +440,7 @@ module axi_ad9001_core #(
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DDS_DISABLE (0),
.DDS_DISABLE (DDS_DISABLE),
.IQCORRECTION_DISABLE (1),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),

29
library/axi_adrv9001/axi_adrv9001_rx.v
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@ -37,6 +37,7 @@
module axi_adrv9001_rx #(
parameter ID = 0,
parameter ENABLED = 1,
parameter CMOS_LVDS_N = 0,
parameter COMMON_BASE_ADDR = 'h00,
parameter CHANNEL_BASE_ADDR = 'h01,
@ -101,6 +102,31 @@ module axi_adrv9001_rx #(
output reg up_rack
);
generate
if (ENABLED == 0) begin : core_disabled
assign adc_rst = 1'b0;
assign adc_single_lane = 1'b0;
assign adc_sdr_ddr_n = 1'b0;
assign adc_r1_mode = 1'b0;
assign adc_valid = 1'b0;
assign adc_enable_i0 = 1'b0;
assign adc_data_i0 = 16'b0;
assign adc_enable_q0 = 1'b0;
assign adc_data_q0 = 16'b0;
assign adc_enable_i1 = 1'b0;
assign adc_data_i1 = 16'b0;
assign adc_enable_q1 = 1'b0;
assign adc_data_q1 = 16'b0;
always @(*) begin
up_wack = 1'b0;
up_rdata = 32'b0;
up_rack = 1'b0;
end
end else begin : core_enabled
// configuration settings
localparam CONFIG = (CMOS_LVDS_N * 128) +
@ -366,6 +392,9 @@ module axi_adrv9001_rx #(
assign adc_single_lane = adc_num_lanes[0];
end
endgenerate
endmodule
// ***************************************************************************

31
library/axi_adrv9001/axi_adrv9001_tx.v
View File

@ -37,6 +37,7 @@
module axi_adrv9001_tx #(
parameter ID = 0,
parameter ENABLED = 1,
parameter CMOS_LVDS_N = 0,
parameter COMMON_BASE_ADDR = 'h10,
parameter CHANNEL_BASE_ADDR = 'h11,
@ -100,6 +101,33 @@ module axi_adrv9001_tx #(
output reg [ 31:0] up_rdata,
output reg up_rack
);
generate
if (ENABLED == 0) begin : core_disabled
assign dac_rst = 1'b0;
assign dac_data_valid_A = 1'b0;
assign dac_data_i_A = 16'b0;
assign dac_data_q_A = 16'b0;
assign dac_data_valid_B = 1'b0;
assign dac_data_i_B = 16'b0;
assign dac_data_q_B = 16'b0;
assign dac_single_lane = 1'b0;
assign dac_sdr_ddr_n = 1'b0;
assign dac_r1_mode = 1'b0;
assign dac_sync_out = 1'b0;
assign dac_valid = 1'b0;
assign dac_enable_i0 = 1'b0;
assign dac_enable_q0 = 1'b0;
assign dac_enable_i1 = 1'b0;
assign dac_enable_q1 = 1'b0;
always @(*) begin
up_wack = 1'b0;
up_rdata = 32'b0;
up_rack = 1'b0;
end
end else begin : core_enabled
// configuration settings
@ -377,6 +405,9 @@ module axi_adrv9001_tx #(
assign dac_single_lane = dac_num_lanes[0];
end
endgenerate
endmodule
// ***************************************************************************