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axi_fmcadc5_sync: define spi clock constraint 

Create the spi clock based on input clock for the worst case scenario.
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Laszlo Nagy 2019-05-20 10:16:55 +01:00 committed by Laszlo Nagy
parent 8390bf0ac6
commit 70d7840c2b
1 changed files with 4 additions and 0 deletions
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library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc
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@ -40,3 +40,7 @@ set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUEN
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
# Define spi clock
create_generated_clock -name spi_clk \
-source [get_pins -hier up_spi_clk_int_reg/C] \
-divide_by 2 [get_pins -hier up_spi_clk_int_reg/Q]