From 70d7840c2b51bf8da23561ec565b5cb37951b976 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 20 May 2019 10:16:55 +0100 Subject: [PATCH] axi_fmcadc5_sync: define spi clock constraint Create the spi clock based on input clock for the worst case scenario. --- library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc index bb240d8f6..54bd99093 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc @@ -40,3 +40,7 @@ set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUEN set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}] +# Define spi clock +create_generated_clock -name spi_clk \ + -source [get_pins -hier up_spi_clk_int_reg/C] \ + -divide_by 2 [get_pins -hier up_spi_clk_int_reg/Q]